Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2001-03-06
2002-06-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S610000, C438S622000, C148S033200
Reexamination Certificate
active
06399959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a structure for manufacturing a metal-induced-laterally-crystallization thin-film transistor, and more particularly to a structure for using insulating gettering layer to reduced metal impurities under the channel region.
2. Description of the Prior Art
A method of crystallizing amorphous silicon using heat treatment at a low temperature after a certain kind of a metal layer has been deposited on the amorphous silicon is know as an MIC and MILC process. The MIC and MILC process is beneficial due to the low temperature crystallization of amorphous silicon. However, the MIC and MILC process has not been applied to electronic devices because of an inflow of metal impurity into the thin film of crystallized polycrystalline silicon formed underneath the metal layer, which cause the electrical characteristics of thin film transistor to deteriorate.
FIGS. 1A
to
1
C show a method of fabricating a channel region of a thin film transistor using an MILC process according to a related art.
Referring to
FIG. 1A
, an amorphous silicon layer
110
, as an active layer is deposited on an insulation substrate
100
having a buffer film (not shown in FIG.) on its upper part, and the active layer
110
is patterned by photolithography and etching process. A gate insulation layer
120
and a gate electrode
130
are formed on the active layer by conventional processes.
Referring to
FIG. 1B
, a nickel layer
140
is formed to a thickness of 10~50 angstrom by sputtering nickel on the entire surface of the formed structure. Then a source region
110
S and a drain
110
D are formed at portions of the active layer by heavily doping the entire surface of the formed structure with impurities. Between the source region
110
S and drain region
110
D, a channel region
110
C are formed on the substrate
100
.
Referring to
FIG. 1C
, amorphous silicon in the active layer is crystallized by heating the substrate
100
at a temperature of 350° C.-600° C. Then the source region
110
S and drain region
110
D on which the nickel layer
140
has been formed become the MIC regions having amorphous silicon crystallized to be polycrystalline silicon by an MIC process. The channel region
110
C without the nickel layer
140
formed directly thereon, becomes the MILC region where silicon has been crystallized to polycrystalline silicon by an MILC process. Dopants are activated in the source region
110
S and drain regions
110
D during the heat treatment as amorphous silicon is crystallized in the active layer.
In the thin film transistor fabricated by the above-described method according to the conventional art, the channel region
110
C has boundaries defined by the polycrystalline structure of silicon in the MIC regions facing that of silicon in the adjacent MILC region. Since the boundary between the MIC region and the MILC region is located at the junction where the source or drain region meets the channel region, an abrupt difference in the crystal structure appears in the junction and the metal from the MIC region contaminates the adjacent MILC region. Consequently, traps are formed at such junctions which cause unstable channel regions and deteriorates the characteristics of the thin film transistor.
The main defect in the conventional method of TFT i.e. metal impurity pollution, causes diffusion in the channel region in the metal crystallization process so that a leakage current is enhance more and more which its own term damages the performance as well as the reliability of the device. Accordingly, there exists a need to provide a way to solve the metal impurity pollution issue for forming an insulating gettering layer with impurity gettering function under the channel region.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a TFT with insulating gettering layer that substantially can be used to solve metal impurity pollution issue in conventional process.
One of the objectives of the present invention is to provide a method to form an insulating gettering layer with impurity gettering function under the channel region.
Another of the objective of the present invention is to provide a method to form an insulating gettering layer with impurity gettering absorbing metal impurity within channel region and reducing the concentration of the metal impurity of channel region.
A further objective of the present invention is to provide a method to form an insulating gettering layer with impurity gettering keeping the temperature low, polycrystalline silicon big and to maintain a high carrier mobility in metal-induced-laterally-crystallization thin-film.
A further another objective of the present invention is to provide a method to form an insulating gettering layer with impurity gettering reducing leakage current to improve device performance and reliability.
In order to achieve the above objects, the present invention provides a structure for forming thin film transistor with reduced metal impurities. The structure at least includes the following steps. First of all, an insulation substrate. Then, an insulating gettering layer on the insulation substrate, wherein the amorphous silicon layer defines an active area, and a channel region on the insulating gettering layer, a source region on the insulating gettering layer adjacent to the channel region, a drain region on the insulating gettering layer adjacent to the channel region and opposite to the source region, and a gate on the channel region, wherein the source, drain, insulating gettering layer and channel region are components of a transistor.
REFERENCES:
patent: 5757063 (1998-05-01), Tomita et al.
patent: 6083324 (2000-07-01), Henley et al.
patent: 6090699 (2000-07-01), Aoyama et al.
Chang Ting-Chang
Chen Ching-Wei
Nelms David
Tran Mai-Huong
United Microelectronics Corp.
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