Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-12-22
2002-08-27
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S120000
Reexamination Certificate
active
06441769
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
N/A
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
This invention relates generally to analog-to-digital converters and more particularly to pipelined analog-to-digital converters having a feed-forward correction signal propagated between stages for providing more accurate digital conversion.
Pipelined analog-to-digital converters (ADCs) are well known in the art. A typical pipelined ADC includes a series of stages, wherein each stage provides one or more output digital bits. The output digital bits from each stage taken together represent the digital value of an input signal provided to the ADC.
FIG. 1
illustrates a typical pipelined ADC
100
having a first stage
102
receiving a signal input, Vin on input line
104
. Each stage provides one or more output digital bits on the outputs
106
and also provides an output residue
108
that is the input for the next stage. The output residue represents the non-digitized portion of the input signal that remains after being processed by each stage. The pipelined ADC, illustrated in
FIG. 1
, includes N stages.
FIG. 2
illustrates a pair of typical prior art pipelined ADC stages. An input signal Vin is provided on line
202
to the first stage
201
where a N-bit ADC
204
samples the input signal and provides a N-bit digital output signal
206
. A N-bit digital-to-analog converter (DAC)
208
samples the N-bit digital output and provides an analog signal
210
that is representative of the digital output signal
206
. A subtraction module
212
subtracts the analog signal
210
from the input signal
202
, and the difference is amplified by amplifier
214
. The amplified difference signal on line
216
is the output residue of that stage. The next stage
203
receives the output residue on line
216
as an input signal and operates as described above.
Although in theory the pipelined ADC should produce nearly perfect digital representations of an input signal, in practice the components and amplifiers that comprise the pipelined ADC are not ideal. In particular, the components comprising the amplifier assemblies
214
and
228
are typically comprised of one or more operational amplifiers along with a plurality of other components such as resistors, capacitors, and switches. It is well known that operational amplifiers have a finite open-loop gain and a gain-bandwidth product that reduces the open-loop gain as the frequency increases. It is not the amplifier assembly
214
or
228
themselves that provide the errors, but rather, the components that comprise these assemblies that provide the errors.
FIG. 3
illustrates a typical amplifier topography of the amplifier block
214
or
228
as a block diagram of a high gain amplifier having a feedback network and a differential input. This configuration allows the amplifier illustrated in
FIG. 3
to combine both the subtraction module
212
and
226
with the amplifier module
214
or
228
respectively in each stage illustrated in FIG.
2
. One skilled in the art should recognize
FIG. 3
as a block diagram of an operational amplifier configured as a difference amplifier with gain. The high gain amplifier with feedback has two inputs Vin
1
301
and Vin
2
303
and two input networks
302
and
305
that couple the respective inputs to a summing module
304
. The output of the summing module
304
is then provided to the high gain amplifier
396
, where the output of the high gain amplifier is sampled and fed back to the summing module
304
by the feedback network
308
. It can be shown that the output voltage of the amplifier in
FIG. 3
can be given as:
V
out
=
V
1
C
B
+
V
2
D
B
-
V
out
A
(
1
)
where A is the open loop gain of the operational amplifier, B is the feedback network transfer function
308
, C is the input network transfer function
302
for the input
301
, and D is the input network transfer function
305
for the input
303
. If A is infinity as is commonly assumed, then the gain equation (1) simplifies to the commonly used operational amplifier gain equation.
However, if high accuracy is required in a particular applications, such as a highly accurate ADC, the non-infinite value of the gain A in the third term of equation (1) will deleteriously impact the accuracy of the output signal. In addition, because the gain, A, of the amplifier
306
rolls off at higher frequencies, high speed applications will suffer an even greater error as the value of the gain, A, in equation (1) is further reduced.
Therefore it would be advantageous to provide a pipelined ADC that did not suffer from the limitations of the operational amplifiers used within the amplifier modules of the pipelined ADC.
BRIEF SUMMARY OF THE INVENTION
An apparatus for correcting for the finite gain of an amplifier assembly in a pipelined analog to digital converter (ADC) is disclosed in which an input signal to an amplifier module of one stage of the pipelined ADC is sampled and provided to the input of an amplifier of a subsequent stage as a feed-forward error correction signal. The feed-forward correction signal is subtracted in the next stage from the output residue signal of the previous stage input to the second subsequent stage amplifier in order to remove part of the output signal from the first stage that includes the finite gain of the amplifier.
The present invention provides for an apparatus for correcting for the non-ideal characteristics of the electronic components that are used to amplify the residue output signal of a stage in a pipelined analog to digital converter (ADC). The resulting pipelined ADC is more accurate and able to operate at higher speeds because the portions of the output residue signal due to the non-ideal characteristics of the electronic components have been removed.
More particularly, a pipelined ADC is comprised of a plurality of stages connected to one another serially, wherein the stage output of one stage provides the stage input for the next subsequent stage. Each stage includes an N-bit ADC having an ADC input coupled to the stage input and an ADC output that provides an N-bit digital output signal representative of the input signal. Each stage further includes a N-bit digital-to-analog converter (DAC) having an input and an output, where the input is coupled to the N-bit digital output signal. The DAC provides an analog output signal representative of the N-bit digital output signal. Each stage further includes a subtraction module that is coupled to the stage input and the analog output signal of the DAC and provides an output to an amplifier having a gain of
2
N
that provides, as an output, the amplified difference signal that is the output residue signal of the stage. A sampling network samples the input signal of the amplifier assembly and provides the inverse of the sampled output signal to the subtraction module of the next subsequent stage to remove that portion of the output residue signal that is due to the non-ideal characteristics of the amplifier module.
REFERENCES:
patent: 4604584 (1986-08-01), Kelley
patent: 4908621 (1990-03-01), Polonio et al.
patent: 5534864 (1996-07-01), Ono et al.
patent: 5635937 (1997-06-01), Lim et al.
patent: 6211806 (2001-04-01), McCarroll
patent: 6323800 (2001-11-01), Chiang
Brady W. James
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Wamsley Patrick
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