Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-11-17
2002-06-18
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S08800C, C174S262000, C029S868000
Reexamination Certificate
active
06407345
ABSTRACT:
TECHNICAL FIELD
This invention relates to a printed wiring board forming a wiring pattern thereon and in particular relates to a printed wiring board able to be suitably used in a multilayer build-up wiring board and a manufacturing method of the printed wiring board.
BACKGROUND ART
A method for alternately building-up an insulating layer and a conductor layer in a core substrate is adopted at present to realize an increase in density of the multilayer printed wiring board. Here, there are two kinds of methods constructed by full additive and semi-additive methods as the built-up method. A manufacturing process of a conductor circuit onto an interlayer resin insulating layer of the multilayer printed wiring board using this semi-additive method will be explained next with reference to FIG.
32
.
First, an insulating layer
250
having an opening
250
a
as a via hole is formed on each of both faces of a core substrate
230
. An electroless plating copper film
252
is uniformly formed on a surface of the interlayer resin insulating layer
250
(FIG.
32
(A)). An unillustrated resist film for forming a resist is adhered onto the electroless plating copper film
252
. Thereafter, the resist film is exposed and developed and a resist
254
for plating is formed (FIG.
32
(B)). Thereafter, an electrolytic plating copper film
256
is deposited in a nonforming portion of the resist
254
by dipping the core substrate
230
into an electrolytic plating liquid and flowing an electric current through the electroless plating copper film
252
(FIG.
32
(C)). Wiring patterns
258
a,
258
b
and a via hole
260
are then formed by separating the resist
254
and separating the electroless plating copper film
252
below the resist
254
by etching. Similar processes are repeated and an interlayer resin insulating layer
350
, a wiring pattern
358
and a via hole
360
are further formed (FIG.
32
(E)).
FIG.
33
(B) shows a B—B section of FIG.
32
(E). At present a design of pulling-out wiring branched from one main wiring is adopted to prevent disconnection in the multilayer printed wiring board. Therefore, a crossing portion X formed in a T-character shape is formed as shown in FIGS.
33
(A) and
33
(B).
However, there is a case in which the wiring pattern is disconnected in the above crossing portion X. Namely, the wiring pattern
258
is formed in the nonforming portion of the resist
254
as mentioned above with reference to FIG.
32
(C). However, as shown by the crossing portion X in FIG.
33
(A), no plating liquid can be sufficiently moved around a corner portion C in which wall faces
258
&bgr;,
258
&bgr; of the wiring pattern
258
in the crossing portion cross at an angle (here a right angle) equal to or smaller than 90°. Accordingly, the wiring pattern is made thin so that disconnection is caused in a particular case.
Further, as shown in FIG.
33
(B), the wiring pattern
258
b
formed by a metal such as copper, etc. is suddenly curved in the crossing portion X. Therefore, a case in which stress is concentrated to the corner portion C of the crossing portion in repetition of thermal contraction and a crack CL is thereby caused in the wiring pattern and the wiring pattern is thus disconnected.
Furthermore, when the wiring pattern
258
b
is coated with the interlayer resin insulating layer
350
as mentioned above with reference to FIG.
32
(E), there is a case whereby an air bubble B is left between the wiring pattern
258
b
and the interlayer resin insulating layer
350
in the corner portion C of the crossing portion as shown in FIG.
33
(B). At this point, when the air bubble B is left in a lower layer of the interlayer resin insulating layer
350
, the air bubble B is expanded in the thermal contraction of the printed wiring board and causes a breakdown of the printed wiring board.
In a further background art of the present invention, a multilayer build-up wiring board is formed by alternately laminating an interlayer resin insulating layer and a wiring layer on a core substrate. The multilayer build-up wiring board is mainly manufactured by an additive method at present. The above wiring layer is formed in an opening portion of a resist formed on the interlayer resin insulating layer by electrolysis or by electroless plating. Upper and lower wiring layers are electrically connected to each other by a via hole extending through the interlayer resin insulating layer. Each of these wiring layers is constructed by a via hole land used as a receiving pan of the via hole, a wiring pattern, a solid portion having a high potential applied by a power source, etc. and having a function similar to the function of a capacitor electrode, etc. Here, minimum values of a size of the via hole land, a width of the wiring pattern and an insulating distance between the via hole land and the wiring pattern are determined by resolution of the resist, an attaching degree of plating, etc. The via hole land and the wiring pattern are manufactured by setting the size, the width and the insulating distance to be greater than these minimum values respectively.
The multilayer build-up wiring board for a package functions as a connector for electrically connecting an electronic part such as an IC chip, etc. mounted to an upper face of the multilayer build-up wiring board to a printed wiring board such as a mother board, etc. located on a lower face of the multilayer build-up wiring board. Here, it is required that a line width of the wiring pattern, an insulating distance and a land diameter are reduced to cope with an increase in density of a connecting portion of the electronic part and the printed wiring board. However, when these values are set smaller than the above minimum values respectively, no desirable wiring can be formed by dispersion of a slight process condition in order that the probability of generation of disconnection of the wiring, a short-circuit of wirings, etc. is increased and yield is reduced.
In contrast to this, it is also possible to cope with the above increase in density by increasing the number of build-up layers of the multilayer build-up wiring board without reducing the line width of the wiring pattern and the insulating distance. However, if the number of build-up layers is increased, a manufacturing process becomes exponentially complicated and reliability and yield are reduced.
Here, in the further background art of the present invention, thick and thin portions of the wiring pattern are formed in the multilayer build-up wiring board of the prior art so that resistance is not uniform and has a inferior influence on propagation of an electric signal. Further, no thickness of an interlayer resin insulating layer (30 &mgr;m) formed on an upper layer of the wiring pattern (having 15 &mgr;m average in thickness) is uniformed so that no electric characteristics of the wiring board can be constantly set. Therefore, it is difficult to improve performance of the multilayer build-up wiring board.
When the inventors of this application investigated this cause, it was found that the thickness of the interlayer resin insulating layer was dispersed by an arranging density of the wiring pattern. For example, there is a case in which the thickness of the interlayer resin insulating layer is thin in a high wiring density portion and is thick in a low wiring density portion (having no signal line therearound). In contrast to this, there is also a case in which the thickness of the interlayer resin insulating layer is thick in a high wiring density portion and is thin in a low wiring density portion.
It is considered from these facts initially that the thickness of the interlayer resin insulating layer is dispersed by plating thickness. In particular, it is considered that the thickness of a signal line is increased in the low wiring density portion since an electric field is concentrated to this low wiring density portion in electrolytic plating. In contrast to this, it is considered that the thickness of the signal line is reduced in the high wiring density portion since the elec
Hirose Naohiro
Kariya Takashi
Mori Yoji
Ibiden Co. Ltd.
Paladini Albert W.
Pillsbury & Winthrop LLP
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