Differential detection receiver

Details Differential detection receiver Differential detection receiver

1999-07-19

2002-05-21

Pham, Chi (Department: 2631)

Pulse or digital communications

Receivers

C375S330000, C708S440000

Reexamination Certificate

active

06393067

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential detection receiver used in a digital radio communication and, more specifically, to simplification of constituent circuits and the entirety of such a receiver.
2. Description of the Prior Art
In order to effectuate differential detection with a high precision in a digital circuit, it is a common practice to multiply a symbol in a signal with a just preceding symbol in the signal by using a multiplier and to subsequently perform an addition or subtraction operation to the obtained product. However, a multiplier requires a large scale circuit and accordingly a large amount of electric power, which is especially true if differential detection is to be achieved at a high speed. For this reason, in order to effectuate differential detection without using a multiplier, there is adopted a scheme in which differential information is detected by finding an arctangent (tan
−1
) of each symbol in a signal from a conversion table and calculating the difference between arctangents of adjacent symbols. Since this scheme fails to reduce the circuit size if the scheme requires a large conversion table, various techniques have been devised which eliminate the need of storing a lot of data in a conversion table.
Japanese Patent No. Sho62-549 (1987) discloses a digital arithmetic circuit which, for a given vector, calculates the magnitude thereof and the angle thereof with a reference coordinate as an inverse trigonometric function or an arctangent by using a reduced-size arctangent conversion table.
Japanese Patent No. Hei6-105,421 (1994) discloses a digital circuit for calculating an inverse trigonometric function or an arctangent of a 2n-bit binary number X. In this system, the calculation is achieved by utilizing the fact that if the binary number X comprises n higher digits H and n lower digits L (X=H+L), then the arctangent of X can be approximated as
arctan(
X
)=arctan(
H
)+
L
/(
H
2
+1).
This system requires two conversion tables for arctan (H) and 1/(H
2
+1) and a multiplier.
Further, in demodulating an input signal, the input signal needs level adjustment. In order to adjust the level of the input signal, the gain of an input signal amplifier is generally controlled by feeding back the result of comparison between a coded output and a reference level to the input signal amplifier.
Japanese Patent unexamined publication No. Hei1-71,270 (1989) discloses a level adjusting device of a just mentioned type. The disclosed device comprises a differential amplifier, an A/D converter, an LPF, a gate, a gate pulse generator, a subtracter, a nonlinear amplifier, an integrator and a D/A converter.
However, the above mentioned arctangent calculating circuits still require conversion tables and multipliers and the last mentioned device requires a D/A converter, which prevents the reduction in size and power consumption of the circuit. Thus, there remain in the prior art some room for improvement to reduce the size and the power consumption of constituent circuits of a differential detection receiver by further simplifying such circuits.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a differential detection receiver with a reduced power consumption by simplifying constituent circuits of the differential detection receiver.
According to an aspect of the invention, an arctangent calculator is realized without using a multiplier or a conversion table.
According to another aspect of the invention, there is realized without using a D/A converter, a level adjusting circuit for adjusting the absolute value of a vector (Ax, Ay) given as input signals Ax and Ay so as to make it one.
According to a further aspect of the invention, a differential detection demodulator with a reduced power consumption is realized by eliminating power consuming circuits such as a multiplier and a large conversion table from the system.
There are described some illustrative embodiments in which a differential detection demodulator has any combination of the features of line (or channel) quality estimation; an improved error rate by means of a soft decision error correction in a channel decoder; elimination of frequency error; improvement of demodulated signal by diversity reception; and demodulated data selection based on an integrated value of phase likelihoods.


REFERENCES:
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patent: 5001727 (1991-03-01), McDavid
patent: 5134631 (1992-07-01), Kingston et al.
patent: 5455847 (1995-10-01), Guilford et al.
patent: 5459683 (1995-10-01), Uesugi et al.
patent: 5657354 (1997-08-01), Thesling, III et al.
patent: 5703526 (1997-12-01), Meyer
patent: 5832041 (1998-11-01), Hulyalkar
patent: 5844943 (1998-12-01), Kazecki et al.
patent: 2234411 (1991-01-01), None
patent: 7-58794 (1995-03-01), None

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