Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2000-10-02
2002-06-25
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making passive device
C438S239000, C438S243000
Reexamination Certificate
active
06410397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dielectric capacitor with a structure preferable in a case where a material such as Pt (platinum) which is hard to have micro lithograph is used as electrode materials, and a method of manufacturing the same, and a dielectric memory using the same.
2. Description of the Related Art
Non-volatile ferroelectric memories using a ferroelectric thin film have been often developed with the recent advances in film making technology these days. The ferroelectric memories are non-volatile Ferroelectric Random Access Memories (FeRAM), which can perform high-speed rewriting by using high-speed polarization inverse of the ferroelectric thin film and the dielectric polarization thereof, and have a characteristic that written contents are not erased when the power is turned off, different from a volatile memory with which written information is erased when the power is turned off.
In conventional products of the ferroelectric memories with 64M level, Pt (platinum) is used as an electrode material to have a stable dielectric characteristic. It is because Pt is hard to be oxidized and so that an oxide layer with high electric resistance will not be easily formed in an interface between a dielectric film and the electrode.
FIG. 1
shows a cross sectional structure of the conventional ferroelectric memory
100
in which Pt is used as an electrode material.
The ferroelectric memory
100
comprises a transistor
100
A and a ferroelectric capacitor
100
B. The transistor
100
A comprises impurity regions
103
A and
103
B which are to be a source or a drain regions formed in an area surrounded by a filed insulator
102
on a surface of a substrate
101
made of such as silicon, and a gate electrode (word line)
105
formed on the substrate
101
between the impurity regions
103
A and
103
B through a gate insulator
104
. The ferroelectric capacitor
100
B has a structure with a lower electrode layer
108
, a ferroelectric film
109
and an upper electrode layer
110
being stacked in this order. The lower electrode layer
108
and the upper electrode layer
10
are formed with Pt respectively. The lower electrode layer
108
is formed on a titanium stacking layer (TiN/Ti)
107
which is formed on a first interlevel insulator
106
. Ti(titanium) film in the titanium stacking layer serves as a contact layer and TiN (titanium nitride) film in the titanium stacking layer serves as a diffusion preventing layer. The titanium stacking layer
107
is connected electrically to the impurity region
103
A through a poly crystal silicon plug layer
111
buried in a contact hole which is provided in the interlevel insulator
106
.
The titanium stacking layer
107
, the lower electrode layer
108
and the ferroelectric film
109
are covered with stacking layers such as TiO
2
film
112
and CVD SiO
2
film
113
so as to prevent diffusion of oxygen. The upper electrode layer
110
is connected to the ferroelectric film
109
through the contact hole provided in the stacking layer. The ferroelectric capacitor
100
B is covered with a second interlevel insulator
114
. A contact hole
115
is provided in the second interlevel insulator
114
and the first interlevel insulator
106
and, through the contact hole
115
, a bit line
116
is electrically connected to the impurity region
103
B.
In this dielectric memory
100
, when a voltage is applied to the gate electrode
105
of the transistor
100
A, the transistor
100
A is turned on and an electric current passes through between the impurity regions
103
A and
103
B. Thereafter, an electric current flows into the dielectric capacitor
100
B through a contact plug layer
111
and a voltage is applied between the upper electrode layer
110
and the lower electrode layer
108
. As a result, polarization occurs in the ferroelectric film
109
. The voltage-polarization characteristic includes hysteresis which is utilized to store and read data of “1” or “0”.
With the ferroelectric memory
100
, there is a problem as follows when forming Pt as an electrode material of the ferroelectric capacitor
100
B. That is, physical etching methods something close to ion milling etching have to be employed, since Pt is hard to be oxidized and stable as electrode materials. However, hard-to-remove deposits and a dirt made from a mixture of resist and platinum pile up when ion milling etching is applied.
FIGS. 2A and 2B
are illustrated to show specific examples.
FIG. 2A
shows a state where a resist film
203
with an electrode pattern is formed on a platinum film
202
provided on a base layer
201
, and the platinum film
202
is selectively removed by milling etching using the resist film
203
as a mask. A deposit
202
a
of platinum and possibly other of the materials are scattered during the etching and attach to sidewalls of the resist film
203
.
FIG. 2B
shows a state where the resist film
203
is removed from the state described above, leaving the deposit
202
a
on the processed platinum layer
202
. Such a state, where the deposit
202
a
remains on the processed platinum layer
202
, is not favorable for micro lithography and is a main reason for hindering a high integration of the ferroelectric memory.
SUMMARY OF THE INVENTION
In view of the above-described problems, the present invention has been made. It is an object of this invention to provide a dielectric capacitor and a method of manufacturing the same, and a dielectric memory using the same, which can be easily processed even a stable material such as platinum is used as electrode materials, so that manufacturing process can be simplified.
The dielectric capacitor of the invention has an interlevel insulator with a trench being formed. In the trench of the interlevel insulator, a structure of stacking layer in which a first electrode layer, a dielectric film and a second electrode layer are stacked in this order, is buried.
Another dielectric capacitor of the current invention has the second interlevel insulator with a trench, and a stacking structure, in which the first electrode layer, the dielectric film and the second electrode layer are stacked in this order, being buried in the trench and has a third interlevel insulator with a contact hole contacting the second electrode layer being formed on the second interlevel insulator and with a sidewall made of insulating materials formed on a wall of the contact hole, and has a wiring layer being formed on the third interlevel insulator electrically connected to the second electrode layer through an area between sidewall films.
A manufacturing method of the dielectric capacitor according to the current invention includes steps of forming the second interlevel insulator with a surface being flattened on a substrate in which a transistor is formed covered with a first interlevel insulator, forming the trench in the second interlevel insulator contacting the transistor, flattening the surface of the trench according to the surface of the second interlevel insulator after stacking the first electrode layer, the dielectric film and the second electrode layer in the trench of the second interlevel insulator in this orderers
To be more specific, the dielectric capacitor is manufactured after forming the trench in the second interlevel insulator, by stacking the first electrode layer, the dielectric film and the second electrode layer on the second interlevel insulator, further, etching the first electrode layer, the dielectric film and the second electrode layer by chemical-mechanical polishing method having the second interlevel insulator as an end point detection layer and flattening the surface of the trench in alignment with the surface of the second interlevel insulator.
The dielectric memory according to the current invention has the transistor formed covered with the first interlevel insulator in a substrate, the second interlevel insulator with the trench provided on the switching device, and the dielectric capacitor having a structure in which the first electrode
Ochiai Akihiko
Tanaka Masahiro
Elms Richard
Owens Beth Elise
Sonnenschein Nath & Rosenthal
Sony Corporation
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