Semiconductor integrated circuit apparatus for performing...

Details Semiconductor integrated circuit apparatus for performing... Semiconductor integrated circuit apparatus for performing...

2000-09-22

2002-08-20

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S144000

Reexamination Certificate

active

06437721

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-269913, filed Sep. 24, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit (IC) apparatus and, more particularly, to an IC apparatus provided with a built-in string resistor to be connected to a bonding pad. The present invention relates to, for example, a semiconductor integrated circuit apparatus for performing DA/AD conversion with high accuracy which is used in an analog mixed digital IC apparatus (microcomputer and the like) provided with built-in circuits such as a digital-analog (DA) conversion circuit and analogdigital (AD) conversion circuit as macrocells.
FIG. 9
is a circuit diagram illustrating an example of conventional DA conversion circuits formed inside an analog mixed digital IC apparatus.
In
FIG. 9
, a DA conversion macrocell
90
has a string resistor comprised of a plurality of resistive elements, connected in series, each with an equal resistance R, a set of switching elements of which the switching is controlled by a digital code input, and an operation amplification circuit A to which a selected output from the set of switching elements is input.
The string resistor is connected at its one end to a first bonding pad
91
to which a first reference potential VREFH is supplied from an outside, and further connected at its the other end to a second bonding pad
92
to which a second reference potential VREFL is supplied from an outside.
Each switching element SW contained in the set of switching elements is connected at its one end to either of one end, a voltage dividing node (tap), and the other end of the string resistor in the DA conversion macrocell
90
. Each switching element SW is commonly connected at its the other end to a (+) input terminal of the operation amplification circuit A. An output terminal of the operation amplification circuit A is connected to a DA conversion output terminal
93
, while being connected to a (−) input terminal thereof as feedback.
Generally a DA conversion output voltage VOUT of the above-mentioned DA conversion macrocell
90
is determined with an upper limit potential VREFH, lower limit potential VREFL, the number of bits of the digital code input and the contents (size) of the code input which are supplied from the outside as follows:
V
OUT=
V
REF
L
+(
V
REF
H−V
REF
L
)×code input/2
n
Assuming, for example, that n=12, VREFH=3V and VREFL=0V, the size of the code input is a value ranging from 0 to (2
n
−1)=4095, and the VOUT has a value ranging from 0.0000V to 2.999267V. In this case, an analog voltage with a weight of 1LSB should be 0.732 mV.
In order to achieve the DA conversion with such high accuracy, it is necessary to prepare measures with respect to not only noises generated from a logic circuit in the IC apparatus but also a voltage drop caused by wiring resistances parasitic on various wires.
That is, in the IC apparatus, all the resistances in passes from a pin of a package to reference potential (VREFH and VREFL) applying nodes via lead frames, bonding wires, internal metal wiring and others cause a voltage drop by currents carried at bottoms, and thereby result in deterioration of DA conversion accuracy.
In particular, the parasitic resistance on the internal metal wiring tends to be grater than others, and to make the resistance low, it is necessary to design the internal metal wiring so that the resistance becomes extremely small. For that, it is considered to design the internal metal wiring with broad widths and short lengths. However, such a design causes increased chip sizes and increased cost, provides a limited condition in chip layout, and therefore becomes a factor very hard to handle.
For example to achieve the resolution under the conditions that VREFH=3 and n=12 bits, accuracy of 0.732 mV/1LSB is needed. When a resistance of the string resistor illustrated in
FIG. 9
is assumed to be 10 k&OHgr;, since 10 k&OHgr;/4096=2.44 &OHgr; corresponds to 1LSB, in order to suppress a conversion accuracy error to be equal to or less than LSB/2, it is necessary to suppress resistances RH and RL of wiring resistances respectively parasitic on reference potential wires
94
and
95
to be almost 1.2 &OHgr;.
When a sheet resistance of aluminum wiring used as the internal metal wiring is 100 m&OHgr;/sheet, the wiring resistance of 1.2 &OHgr; requires twelve sheets. When the width of the aluminum wiring is 20 &mgr;m, the length thereof is 240 &mgr;m.
Meanwhile in order to achieve the wiring resistance as described above taking wiring inside a chip into consideration, it is required to bring the D/A conversion macrocell
90
very close to bonding pads
91
and
92
, and to connect those with a shortest distance using metal wiring to shorten the metal wiring between the bonding pads
91
and
92
and DA conversion macrocell
90
.
However, actualizing the wiring is difficult in which the D/A conversion macrocell
90
is arranged very close to the bonding pads
91
and
92
and the sheet resistance of the wiring is not more than an allowance, because of limitations in chip size, positions of bonding pad sections, position of the DA conversion macrocell
90
inside the IC apparatus and pattern layout including other digital circuit sections. In other words, there is a trade-off relationship between the pattern layout (cost) and an extent of deterioration of accuracy caused by the parasitic wiring resistance with equal to or more than the allowance.
FIG. 10
is a characteristic chart showing a potential distribution of the string resistor section in FIG.
9
.
In the figure, a thick line shows a characteristic example when a sufficient decrease of a resistance of an internal wire is not achieved, and a thin line shows an ideal characteristic.
FIG. 11
is another characteristic chart showing an example of relationships between a code input (tap position) and conversion error in the DA conversion macrocell
90
in FIG.
9
.
Accordingly, when the sufficient decrease of the resistance of the internal wire is not achieved as the conventional example as described above, as shown with the thick line in
FIG. 10
, the potential distribution of the string resistor section is not linear. Therefore a DA conversion output voltage VOUT is not. laid in an original range of VREFL to VREFH, shows a characteristic indicative of a reduced range, and thereby causes the deterioration of accuracy (change in errors) as shown in FIG.
11
.
FIG. 12
is a block diagram illustrating a DA conversion circuit according to another conventional example.
In this DA conversion circuit, correction data to correct conversion errors are stored in advance, for example, in a correction data RAM
120
. In outputting by DA conversion, the correction data is read with respect to the DA conversion output from an original DAC (DA converter)
121
, and an output buffer circuit
123
performs a correction operation on an output subjected to DA conversion in correcting DAC
122
, and outputs a corrected output VOUT.
This DA conversion circuit is effective in preventing the accuracy deterioration caused by a difference between a designed value and actual resistance of the string resistor in the DAC
121
. However the DA conversion circuit has problems that a configuration of the circuit is complicated, and that another accuracy deterioration is not prevented which is caused by a voltage drop of the reference voltage due to the wiring resistance as described previously.
As described above, the conventional semiconductor integrated circuit apparatus has had the problem that the linearity of a potential distribution of a string resistor section deteriorates, which occurs when a wiring resistance is equal to or more than an allowance which is parasitic on a reference potential wire between a reference potenti

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