Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-09-01
2002-06-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S185010, C365S189120, C710S010000, C710S314000
Reexamination Certificate
active
06407960
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to initialization of devices, for example network interface controller devices or integrated network switch devices, using a read only memory device such as an EEPROM.
2. Background Art
Complex chip devices such as Ethernet (IEEE 802.3) controllers typically have control registers that need to be programmed with values for operation. One arrangement for loading the values into the registers is to store the values on-chip during chip fabrication by hardwiring the values using gate transistors. The hardwiring of values on the chip, however, severely restricts the flexibility in programming the registers during power on reset: designers of the device may have selected hardwired values that are different from values preferred by users of the device. Hence, users of the device may need to overwrite the default values using a processor unit such as a central processing unit (CPU) as a host for the device. Use of a host CPU, however, increases the cost of a system.
Chip devices also may include an EEPROM interface for programming of the chip. For example, the commercially-available Am79C972 PCne™−FAST+10/100 Mbps PCI Ethernet Controller from Advanced Micro Devices, Inc. of Sunnyvale, Calif., includes an EEPROM interface for programming the controller using an EEPROM. In particular, the Am79C972 Data Sheet specifies that the Am79C972 controller EEPROM interface includes EEPROM detection circuitry configured for detecting the presence of an attached EEPROM in response to a reset of the device (e.g., deassertion of a reset pin). If the detection circuitry detects a connected EEPROM, the EEPROM interface automatically begins to read serial data via from the EEPROM via a single data pin into prescribed registers according to a prescribed read sequence, illustrated typically using an EEPROM map. Hence, the Am79C972 controller can be programmed automatically using an EEPROM.
The automatic programming of a chip device using an EEPROM, however, still assumes that only certain device registers are programmed in a prescribed read sequence as specified by the corresponding EEPROM map. For example, a chip designer may assume that a first fixed set of registers should not be specified in the EEPROM map because they should be loaded only once with hardwired values upon reset, and that a second fixed set of registers should be specified in the EEPROM map because they should be accessible by the user for overwriting the default values. The assumptions by the designer may not be entirely correct, such that the hardwired values loaded into the first fixed set of registers (i.e., those registers not specified in the EEPROM map) may not be the values desired by the user. Hence, users may still need a host CPU to overwrite the hardwired default values for registers that are not specified within the EEPROM map.
SUMMARY OF THE INVENTION
There is a need for an arrangement that enables any register within a chip device to be selectively programmed by an external memory, such as an EEPROM.
There is also a need for arrangement that enables users to program registers of an integrated device during device initialization without the necessity of programming an external memory, such as an EEPROM, according to a prescribed device register map that specifies programming of the registers in a prescribed sequence.
These and other needs are attained by the present invention, where an integrated device includes an external memory interface that includes address decoding logic configured for identifying a destination device register based on register address information retrieved from an external memory. The external memory interface, upon identifying the destination device register, loads the destination device register with register data read from the external memory, for example contiguously following the corresponding register address information. Hence, the integrated device can be programmed on a per register basis, without the necessity of an EEPROM map.
One aspect of the present invention provides a method in an integrated device. The method includes reading from an external memory a register address value that identifies a destination device register within the integrated device, and reading from the external memory a register data value for the identified destination device register. The method also includes storing the register data value in the destination device register based on the corresponding register address value. The reading of the register address value from the external memory enables users of the integrated device to enjoy maximum flexibility in choosing the registers to initialize. In addition, the storing of the register data value based on the corresponding register address value enables the device to be programmed, using an external memory, without the necessity of prescribed memory mapping schemes such as an EEPROM map.
Another aspect of the present invention provides an integrated device comprising a plurality of device registers each having a corresponding register address value, and an external memory interface. The external memory interface is configured for reading register data values from an external memory, and includes address decoding logic configured for identifying for each read register data value a corresponding one of the device registers based on reading the corresponding register address value from the external memory. Hence, the device registers can be selectively programmed based on reading the register address values from the external memory.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.
REFERENCES:
patent: 5884027 (1999-03-01), Garbus et al.
patent: 5953335 (1999-09-01), Erimli et al.
patent: 6185630 (2001-02-01), Simmons
AMD, “PCnet™-FAST+Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support”, Feb. 1998, Publication No. 21485, pp. 1-4 and 85-87.
Egbert Chandan
Kaniz Marufa
Advanced Micro Devices
Le Vu A.
Turkevich Leon R.
LandOfFree
Arrangement for programming selected device registers during... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement for programming selected device registers during..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement for programming selected device registers during... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2900928