Programmable relaxation oscillator

Details Programmable relaxation oscillator Programmable relaxation oscillator

1999-04-30

2002-04-23

Kinkead, Arnold (Department: 2817)

Oscillators

Solid state active element oscillator

Transistors

C331S143000, C331S144000, C331S11300A, C331S03600C, C331S034000

Reexamination Certificate

active

06377129

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a voltage- or current-controlled oscillator and, more particularly, relates to a voltage- or current-controlled relaxation oscillator having a programmable gain.
BACKGROUND OF THE INVENTION
Many electrical and computer applications and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop (“PLL”) is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a reference or input signal. Wireless communication devices, frequency synthesizers, multipliers and dividers, single and multiple clock generators, and clock recovery circuits are but a few examples of the manifold implementations of PLLs.
Frequency synthesis is a particularly common technique used to generate a high frequency clock from a lower frequency reference clock. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency input (off-chip) clock, typically in the range of 1 to 4 MHz, to generate a high frequency output clock, typically in the range of 10 to over 200 MHz, that is precisely synchronized with the lower frequency external clock. Another common use of PLLs is recovery of digital data from serial data streams by locking a local clock signal onto the phase and frequency of the data transitions. The local clock signal is then used to clock a flip-flop or latch receiving input from the serial data stream.
FIG. 1
is a block diagram of a typical PLL
10
. PLL
10
comprises phase/frequency detector
12
, charge pump
14
, loop filter
16
, voltage-controlled oscillator (“VCO”)
18
and frequency divider
20
. PLL
10
receives a reference clock signal CLK
REF
and generates an output clock signal CLK
OUT
aligned to the reference clock signal in phase. The output clock frequency is typically an integer (N) multiple of the reference clock frequency; with the parameter N set by frequency divider
20
. Hence, for each reference signal period, there are N output signal periods.
Phase/frequency signal detector
12
receives on its input terminals two clock signals CLK
REF
and CLK*
OUT
(CLK
OUT
, with its frequency is divided down by frequency divider
20
). In a conventional arrangement, detector
12
is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, detector
12
generates one of three states. If the phases of the two signals are aligned, the loop is “locked”. Neither the UP nor the DOWN signal is asserted and VCO
18
continues to oscillate at the same frequency. If CLK
REF
leads CLK*
OUT
, than VCO
18
is oscillating too slowly and detector
12
outputs an UP signal proportional to the phase difference between CLK
REF
and CLK*
OUT
. Conversely, if CLK
REF
lags CLK*
OUT
, than VCO
18
is oscillating too quickly and detector
12
outputs a DOWN signal proportional to the phase difference between CLK
REF
and CLK*
OUT
. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals.
Charge pump
14
generates a current I
CP
that controls the oscillation frequency of VCO
18
. I
CP
is dependent on the signal output by phase/frequency detector
12
. If charge pump
14
receives an UP signal from detector
12
, indicating that CLK
REF
leads CLK*
OUT
, I
CP
is increased. If charge pump
14
receives a DOWN signal from detector
12
, indicating that CLK
REF
lags CLK*
OUT
, I
CP
is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals are aligned, charge pump
14
does not adjust I
CP
.
Loop filter
16
is positioned between charge pump
14
and VCO
18
. Application of the charge pump output current I
CP
to loop filter
16
develops a voltage V
LF
across filter
16
. V
LF
is applied to VCO
18
to control the frequency of the output clock signal. Filter
16
also removes out-of-band, interfering signals before application of V
LF
to VCO
18
. A common configuration for a loop filter in a PLL is a simple single-pole, low-pass filter that an be realized with a single resistor and capacitor.
The oscillator is the subject of the present invention. VCO
18
generates an oscillating output signal CLK
OUT
having a frequency proportional to the voltage V
LF
applied to VCO
18
. Conventional voltage-controlled oscillators typically oscillate about a specific center frequency and have a relatively narrow frequency range or bandwidth. When CLK
REF
leads CLK*
OUT
, charge pump
14
increases I
CP
to develop a greater V
LF
across loop filter
16
which, in turn, causes VCO
18
to increase the frequency of CLK
OUT
. Conversely, When CLK
REF
lags CLK*
OUT
, charge pump
14
decreases I
CP
to develop a lesser V
LF
across loop filter
16
which, in turn, causes VCO
18
to decrease the frequency of CLK
OUT
. When CLK
REF
and CLK*
OUT
are aligned, V
LF
is not adjusted, and the oscillation frequency of VCO
18
is kept constant. In this state, PLL
10
is in a “locked” condition.
The output clock signal is also looped back through (in some applications) frequency divider
20
. The resultant output CLK*
OUT
is provided to phase/frequency detector
12
to facilitate the phase-locked loop operation. Frequency divider
20
facilitates comparison of the generally higher frequency output clock signal with the lower frequency reference clock signal by dividing the frequency of CLK
OUT
by the multiplication factor N. Divider
20
may be implemented using trigger flip-flops, or through other methods familiar to those of ordinary skill in the art. Thus, PLL
10
compares the reference clock phase to the output clock phase and eliminates any detected phase difference between the two by adjusting the frequency of the output clock.
Fully monolithic phase-locked loops formed from complementary metal-oxide-semiconductor (“CMOS”) field effect transistors (“FET”) are widely used in many applications. The widespread industrial capability to mass-produce CMOS circuits facilitates the manufacture of inexpensive basic tuning devices employing PLLs for products such as wireless telephones. Since the power consumption of the PLL derives primarily from the on-chip oscillator, the power consumed by the PLL increases as the operating frequency of the oscillator increases. The goal of achieving high frequency operation is thus inconsistent with low power consumption. In addition to lower power consumption, an oscillator having a wide linear range is desirable for optimal PLL performance. Accordingly, there is a need for a low power, high frequency oscillator that has a wide linear range and is designed with CMOS technology.
FIGS. 2
a
,
2
b
and
2
c
depict three CMOS oscillator architectures.
FIG. 2
a
depicts a CMOS-based differential ring oscillator
30
. Ring oscillator
30
is comprised of a plurality of differential inverters
32
connected in cascade, with the output of the last inverter in the series being connected to the input of the first inverter. This oscillator design is problematic in that it is very sensitive to process and temperature variations. The nominal output frequency of a conventional CMOS differential ring oscillator, for example, may range from 700 MHz to 1.3 GHz. This represents almost a 100% frequency variation. This sensitivity stems from the inverse relationship between the delay time of the inverters and the output frequency. A PLL based on a ring oscillator requires an increased VCO gain in order to obtain the necessary range to deal with these wide frequency variations. The increased VCO gain leads to poor phase performance and increased sensitivity.
FIG. 2
b
depicts a typical relaxation oscillator
40
having a grounded timing capacitor
42
. Current sources
46
and
48
together provide a switching current i=±kv
in
, where v
in
is a control vol

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