Wafer level method of capping multiple MEMS elements

Details Wafer level method of capping multiple MEMS elements Wafer level method of capping multiple MEMS elements

2000-11-15

2002-09-10

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S051000, C438S055000, C438S455000, C438S458000, C156S182000, C156S299000

Reexamination Certificate

active

06448109

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the provision of protective caps on microelectromechanical systems (MEMS), and more particularly to capping multiple MEMS that are provided on a common wafer.
2. Description of the Related Art
MEMS, also referred to as micromachines or micro systems, are complete units that contain both electrical and mechanical microstructures with characteristic sizes generally ranging from nanometers to millimeters. They evolved from the photolithographic techniques used to fabricate integrated circuits, and therefore are very small in size and capable of being manufactured in large, inexpensive quantities. Multiple MEMS are typically fabricated on a common semiconductor wafer, in a manner analogous to integrated circuits. They have numerous applications in fields such as physics, chemistry, engineering, biology and medicine.
It is generally necessary to provide a protective cap on a MEMS element. Without protective caps, malfunctions can result from moisture entering the MEMS cavity, and the devices are subject to outgasing and contamination problems.
One approach to capping has been to provide rings of glass or solder paste on a cap wafer that is ultimately diced along with the MEMS wafer into individual chips. The rings form a protective seal around each MEMS when the cap wafer is bonded to the MEMS wafer. However, electrode pads to which electrical wires can be bonded to provide electrical access to the MEMS are also typically provided on the surface of the MEMS wafer. To access these pads after the cap wafer has been put in place, holes have been etched into the cap wafer prior to bonding it to the MEMS wafer. Alternately, access openings in the cap wafer can be partially etched from one side of the wafer prior to bonding to the MEMS wafer, followed by back grinding the opposite side of the cap wafer after bonding to complete the openings. Once the cap wafer has been put in place and the access openings are completed, the joined wafers are diced into individual parts.
A problem with etching access openings all the way through the cap wafer, prior to bonding, is that it makes the cap fragile and subject to breakage, while partially pre-etching the cap wafer and then back grinding after the capping is completed takes a long time. The problem is aggravated for MEMS which include electrical circuitry on the MEMS wafer, in which case there is often also a need to access trimming pads as well as wire bond pads. Furthermore, if there are imperfections in one or more of the seal rings on the cap wafer, its associated MEMS will not be adequately sealed and will have to be discarded along with the cap, reducing the manufacturing yield.
Another problem is that, if the MEMS and cap wafers are formed from different materials with a significant differential between their thermal coefficients of expansion, the relatively high bonding temperatures can result in excessive material strains.
Caps that include active circuitry have also been diced and then bonded one-at-a-time onto respective MEMS of the MEMS wafer. The bonding is accomplished with a “flip-chip” technique in which conductive “bumps” connect corresponding pads on the caps and MEMS wafer, with a solder ring seal around each MEMS. An example of this technique is described in Mayer and Paul, “Flip-Chip Packaging for Thermal CMOS Anemometers”, Proc. IEEE Microelectromechanical Systems, Jan. 26-30, 1997, pages 203-208. This is a slow, manual process in which there is a high breakage risk, since a force must be applied to hold the cap chips to the MEMS wafer at an elevated temperature for a relatively long period of time. The caps can be difficult to precisely align with the underlying MEMS devices, further reducing yields.
SUMMARY OF THE INVENTION
The invention provides a new method of capping MEMS on a common wafer which reduces the risk of breaking the caps and also the amount of cap material needed, leaves trimming and wire bond pads on the MEMS wafer easily accessible, is quick and inexpensive, provides an improved yield and eliminates the alignment problem previously encountered in bonding discrete cap chips to a MEMS wafer.
These improvements are achieved with a new MEMS capping method in which a fixed spatial array of discrete, mutually spaced caps is established for a plurality of MEMS on a common wafer, with the caps positioned at locations corresponding to the positions of the MEMS, and then simultaneously bonding the caps to corresponding MEMS on the wafer. The caps are positioned in the array by a common cap holder that preferably comprises a template with an array of recesses for individual caps. Once bonding has been completed, the wafer is diced into individual MEMS chips.
Protective ring seals are provided on the caps before they are bonded to the MEMS wafer. This allows the caps and ring seals to be inspected individually, with any caps that do not pass the inspection discarded prior to bonding. The method is applicable to both flip-chip bonded caps, and caps that either have no active circuitry or that include circuitry that faces away from the MEMS and is wire bonded to the MEMS wafer. To facilitate a rapid placement of caps in their respective template recesses, while still aligning them accurately with their respective MEMS, the side walls of the recesses can be sloped outwards.
These and other features and advantages of the invention will be apparent to those skilled in the art, taken together with the accompanying drawings, in which:


REFERENCES:
patent: 5824186 (1998-10-01), Smith et al.
patent: 6297072 (2001-10-01), Tilmans et al.
F. Mayer, O. Paul, and H. Baltes, “Flip-Chip Packaging for Thermal CMOS Anemometers”, Proc. IEEE Microelectromechanical Systems, Jan. 26-30, 1997, pp. 203-208.

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