Rigid adhesive underfill preform, as for a flip-chip device

Details Rigid adhesive underfill preform, as for a flip-chip device Rigid adhesive underfill preform, as for a flip-chip device

1999-06-22

2002-06-04

Copenheaver, Blaine (Department: 1773)

Stock material or miscellaneous articles

Structurally defined web or sheet

Including aperture

C439S067000, C174S054000, C174S255000, C174S256000

Reexamination Certificate

active

06399178

ABSTRACT:

The present invention relates to an underfill preform and, in particular, to an adhesive underfill preform and to electronic devices including an adhesive underfill.
Since the invention of integrated circuits in early 1960's, their use has proliferated and they have become indispensable to the multitude of electronic products that modem society has come to rely on and take for granted. While there are many methods of packaging circuits and other semiconductor chips into functional form, their usefulness is greatly enhanced if the physical size of such packaged electronic devices is small and the cost of such packaged devices is low.
Traditionally, connections to semiconductors are made with fine gold or aluminum bond wires that loop from contact pads arranged around the periphery of the top surface of the semiconductor chip (i.e. the side of the chip on which the electronic circuit has been formed) to a lead-frame, header or other package or substrate to which the bottom surface of the semiconductor chip is attached. The technology of bond wire interconnection has been perfected to such a degree that the cost of each bond wire connection is less than one cent ($0.01 U.S.). The electrical characteristics of thin bond wires looping even over a relatively short distance necessarily introduce unwanted inductance and capacitance into the interconnection and thus reduce the bandwidth and operating rate of the electronic devices. This limitation has become more significant in recent years as a result of the development of much faster microprocessors and higher frequency signal processing and communication devices.
One way to reduce the capacitance and inductance of these interconnections is to shorten the length of the interconnection path. One effective conventional way to accomplish this is by flipping the semiconductor chip over (thus, the appellation “flip chip”) so that the contact pads are immediately adjacent to the substrate built on which are formed a corresponding set of contact pads to which the contact pads of the semiconductor may be joined directly. U.S. Pat. No. 3,429,040 entitled “Method of Joining a Component to a Substrate” issued to L. F. Miller describes a flip chip arrangement in which the semiconductor chip is attached to the substrate by solder bumps. The distance between the flip chip and the substrate has been reduced to about 50-100 microns and thereby to enable operation at dramatically higher frequencies.
There are many conventional ways of depositing solder or conductive adhesives for the bonding of electronic components and flip chip semiconductor devices to substrates, such as those set forth, for example in U.S. Pat. No. 3,401,126 entitled “Method of Rendering Noble Metal Conductive Composition Non-Wettable by Solder”, U.S. Pat. No. 3,429,040 entitled “Method of Joining a Component to a Substrate”, U.S. Pat. No. 4,113,981 entitled “Electrically Conductive Adhesive Connecting Arrays of Conductors’, U.S. Pat. No. 5,074,947 entitled “Flip-Chip Technology Using Electrically Conductive Polymers and Dielectrics”, U.S. Pat. No. 5,196,371 entitled “Flip Chip Bonding Method Using Electrically Conductive Polymer Bumps”, U.S. Pat. No. 5,237,130 entitled “Flip Chip Technology Using Electrically Conductive Polymers and Dielectrics”, and U.S. Pat. No. 5,611,140 entitled “Method of Forming Electrically Conductive Polymer Interconnects on electrical Substrates”. One problem common to these prior art techniques is that they all require operations that are substantially different from those normally associated with semiconductor fabrication. As a result, a substantially different kind of process is being employed and a new business has evolved in which service companies perform solder deposition onto semiconductor wafers as well as adhesive deposition onto such wafers.
The interconnection of semiconductor devices in flip chip configuration has evolved from the use of very elaborate metallization and metallurgy to form a conductive bump of suitable height to which connection may be made, to the use of a less demanding and inexpensive solder bump. Soldering and solder-bump technology and metallurgy may be changed in known manner to accommodate changes in composition and methods of depositions suitable for lower and higher temperature reflow soldering of such interconnections. The inherent limitation of solder bump technology has become apparent when semiconductor devices are sought to be directly attached to an organic substrate due to the differences in the coefficient of thermal expansion (CTE) of the materials. For example, FR-4 fiberglass substrates have a CTE of 17 ppm/° C. whereas the semiconductor chip has a CTE of 3 ppm/° C. Substantial limitations similarly arise when the size of the semiconductor chip is greater than five millimeters (5 mm) on each edge, even when the flip chip interconnection is made to an alumina substrate which has a CTE of only 7 ppm/° C. The solder joints have a modulus of elasticity of about 10,000,000 psi and so have very little compliance, thereby rendering the solder connections subject to fatigue failures when subjected to cyclical temperature excursions.
Alternatives to solder-based interconnections have been employed. U.S. Pat. No. 4,113,981 entitled “Electrically Conductive Adhesive Connecting Arrays of Conductors” issued to Fujita et al. describes a non-conductive adhesive base that is filled with too few conductive particles to render it conductive, except where it may be compressed. Fujita et al. describes using such adhesive to attach raised contacts where normally non-contacting conductive particles in the non-conductive adhesive are pressed against raised contacts of a device so that the raised contacts of the device are in electrical contact with the raised contact pads of the substrate and where isolation between laterally adjacent contacts is maintained by the insulating resin. In a conventional semiconductor wafer, the contact pads, normally formed of aluminum, are recessed below the final insulating inorganic passivation layer. One of the limitations of the Fujita patent is that the contact pads must extend above the top of the insulating passivation layer or substrate. This additional preparation, either as part of the semiconductor wafer fabrication or as a separate process, tends to increase the cost of the semiconductor device and, therefore, the interconnection. Another limitation of the Fujita interconnection is that only a limited number of conductive paths may be formed within each conductive contact, so that electrical isolation between only a few of the conductor particles can render the interconnection non-conductive, and, therefore, useless.
Isotopically conductive adhesives have long been used for bonding the backside of the semiconductor die to a package before the contact pads of the die are wire-bonded to the package leads and have also found extensive use to attach semiconductor components, chip resistors and chip capacitors in hybrid circuit assemblies and in printed wiring board assemblies. But conductive adhesive connections also impose requirements on the semiconductor wafer fabricators and on circuit board manufacturers that may differ from their normal processing.
An early usage of conductive adhesive for flip chip bonding is suggested by Scharf et al. in an article entitled “Flip-Component Technology”, published in the Proceedings of IEEE Electronic Component Conference, 1967 (pp. 269-275). Therein, conductive adhesive bumps were stenciled onto a substrate having an array of sixteen bond pads for each semiconductor die that was to be bonded. Scharf et al. focus on how to create a better stencil for printing precision bumps and state certain advantages of using conductive adhesive, such as lower temperature bonding and lower cost. Subsequently, U.S. Pat. No. 4,442,966, entitled “Method of Simultaneously Manufacturing Multiple Electrical Connections Between Two Electrical Elements” issued to P. Jourdain et al. describes the use of conductive paste for bonding aluminum pads on a semiconductor to

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