Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-12-14
2002-04-16
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000, C257S773000, C438S624000
Reexamination Certificate
active
06373136
ABSTRACT:
This application is based on Japanese Patent Application 2000-113286, filed on Apr. 14, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a wiring structure and a semiconductor device with a wiring structure, and more particularly to a damascene wiring structure and a semiconductor device having a damascene wiring structure.
b) Description of the Related Art
Al or Al alloy is often used as a metal wiring material of semiconductor devices. Al and Al alloy have a low resistivity, and are easy to be patterned by using a photoresist mask and etchant gas.
Wiring material having a lower resistivity and a higher allowable current density is desired in order to meet requirements for micro patterns and high speed operation of recent semiconductor devices. Attention has been paid to Cu as such wiring material. If a Cu wiring layer is etched, this etching generates corrosion because of influence of etchant and water contents. Patterning using a photoresist mask and etchant is, therefore, not suitable for a Cu wiring layer. A damascene process is used for patterning a Cu wiring layer (or wiring pattern). A Cu wiring layer is buried in a preformed trench and thereafter an unnecessary area is removed by polishing.
In order to connect a lower level wiring and an upper level wiring, a via conductor is used which is buried in a via hole formed through the interlayer insulating film. If the via conductor and the upper level wiring are formed by different processes, a total process time prolongs. In order to shorten the total process time, a dual damascene process is adopted. With this process, metal is buried or embedded in a trench defined by a via hole formed between multi-layer wirings and a trench for the upper wiring, and thereafter polished to leave the metal only in the trench.
The dual damascene process applied to a Cu wiring layer is, however, associated with wiring defects such as wiring disconnection.
FIGS. 20A
to
20
D show examples of wiring defects formed when a conventional Cu dual damascene process is used.
FIG. 20A
shows an example of a Cu multi-layer wiring structure. A narrow lower wiring layer trench is formed in a lower level insulating film
104
, and a Cu lower wiring
105
is formed in this lower wiring trench. For example, after a barrier metal layer and a seed metal layer are deposited by sputtering, a Cu wiring layer is formed thereon by electrolytic plating. Cu deposited on the upper surface of the lower insulating film
104
is removed by chemical mechanical polishing (CMP). After the lower level wiring
105
is formed, an interlevel insulating film is deposited, the insulating film being a lamination of an SiN layer
106
, an SiO
2
layer
107
, an SiN layer
116
and an SiO
2
layer
117
. In this interlayer insulating film, a via hole
108
for connection of wirings is formed. After the via hole
108
is buried or filled with resist or the like, the SiO
2
layer
117
and SiN layer
116
are selectively removed to form a wide upper wiring layer trench.
After the upper wiring layer trench and via hole
108
are exposed, a via conductor
109
and an upper wiring
110
are formed by the same conductive layer forming process. For example, after a barrier metal layer is deposited by sputtering, a Cu wiring layer is formed on the barrier metal layer by electrolytic plating. Cu deposited on the surface of the SiO
2
layer
117
is removed through polishing. In this manner, a dual damascene wiring DD made of the via conductor
109
and upper wiring
110
can be formed. After the upper wiring
110
is formed, an upper insulating layer is formed on the surface of the dual damascene wiring, the upper insulating film being a two-layered film of an SiN layer
111
and an SiO
2
layer
112
.
A multi-layer wiring structure of Cu wirings is formed in this manner. The via conductor
109
for connection of wirings is made of the same material as the upper wiring
110
.
Such a multi-layer wiring structure may have wiring defects such as wiring disconnection. The wiring defects such as disconnection are often formed in the via conductor in the via hole or the lower Cu wiring near the via hole.
FIG. 20B
is a schematic diagram showing the structure of a wiring defect with a void
120
being formed in the middle of the via hole
108
. This void
120
formed in the middle of the via hole
108
electrically disconnects the lower wiring
105
and upper wiring
110
.
FIG. 20C
is a schematic diagram showing the structure of a wiring defect with a void
120
being formed on the bottom of the via hole
108
. Although the position of the void
120
is different, the lower wiring
105
and upper wiring
110
are electrically disconnected. A void is formed not only in the via hole but also between the via conductor and lower wiring.
FIG. 20D
is a schematic diagram showing a void
120
formed in the lower wiring in the connection area between the via conductor
109
and lower wiring
105
. This void
120
formed in the contact area with the lower wiring
105
electrically disconnects the lower wiring
105
and via conductor
109
.
In the multi-layer wiring structure formed by the dual damascene process, a void which causes wiring defects is often formed in the via conductor or in the surface layer of the lower wiring in the contact area with the via conductor. It is desired to avoid such wiring defects in order to form a highly reliable multi-layer wiring structure.
As above, it is known that if the dual damascene structure is applied to the multi-layer wiring structure of Cu, wiring defects are generated and the reliability is lowered.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a highly reliable damascene wiring structure and a semiconductor having such a damascene wiring structure.
It is another object of the present invention to provide a multi-layer wiring structure capable of shortening a total process time and preventing a void from being formed and a semiconductor device having such a multi-layer wiring structure.
According to one aspect of the present invention, there is provided a damascene wiring structure, comprising: a lower wiring structure; an interlayer insulating film covering the lower wiring structure; a wiring layer trench formed in the interlayer insulating film from an upper surface thereof, and a via hole passing through the interlayer insulating film from a lower surface of the wiring trench in an inner area thereof and reaching the lower wiring structure, the via hole having a diameter smaller than a width of the wiring layer trench; an insulating pillar pattern projecting upward from the lower surface of the wiring layer trench in an area outside of the via hole, the insulating pillar pattern being made of a same material as the interlayer insulating film, wherein a first occupied area factor of the insulating pillar pattern in a first area of the wiring layer trench near to the via hole is higher than a second occupied area factor of the insulating pillar pattern in a second area of the wiring layer trench remote from the via hole; and a dual damascene wiring formed by filling the wiring layer trench and the via hole with conductive material.
According to another aspect of the invention, there is provided a semiconductor device, comprising: a semiconductor substrate; an integrated circuit structure formed on the semiconductor substrate; a multi-layer wiring structure formed above the integrated circuit structure; and a number of pads formed on the semiconductor substrate, wherein the multi-layer wiring structure comprises: a lower wiring structure; an interlayer insulating film covering the lower wiring structure; a wiring layer trench formed in the interlayer insulating film from an upper surface thereof, and a via hole passing through the interlayer insulating film from a lower surface of the wiring trench in an inner area thereof and reaching the lower wiring structure, the via hole having a diameter smaller than a width
Otsuka Satoshi
Yamanoue Akira
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