Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2000-03-07
2002-09-17
Allen, Stephone (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S294000
Reexamination Certificate
active
06452149
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing device and an image input device for an image signal formed into one chip which includes a MOS type solid image sensing device.
In recent years, the MOS type solid image sensing device has been used as various image input devices. In particular, an image sensing element of a type referred to as a CMOS type image sensing element which is fabricated by the CMOS manufacturing technique has widely been used. Most of integrated circuit elements other than the image sensing element are also fabricated by the same CMOS manufacturing technique as in the CMOS type image sensing device. In a CMOS type image sensing device chip, therefore, it is possible to integrate, on the same chip, other integrated circuit elements, particularly, a digital signal processing circuit and a memory element as well as the image sensing element. In recent years, an image input device which is small-sized and consumes less power has been required.
FIG. 1
shows an example of a structure of a conventional image input chip fabricated to meet such a demand. An image input chip
10
comprises an image input section
11
and a signal processing section
12
.
The image input section
11
includes an array of pixel
14
in which a plurality of pixels
13
having a CMOS type photoelectric converting element for converting incident light into an electric signal (an analog signal), for example, are arranged in a matrix, and a plurality of analog to digital (A/D) converters
15
for converting the analog signal converted by the pixels
13
into a digital signal and outputting the digital signal.
The signal processing section
12
is provided for the A/D converter
15
by one to one, and includes a plurality of processing elements (PE)
16
for carrying out a signal processing by using the digital signals output from the A/D converters
15
and a signal output circuit
17
for outputting the result of the processing performed by the PE
16
to the outside of the chip. Each of the PEs
16
in the signal processing section
12
carries out a signal processing according to an instruction generated by a controller
18
.
The analog signal converted by the pixel
13
in the array of pixel
14
is sequentially converted into a digital signal by the A/D converters
15
in a row unit, and is transmitted to the signal processing section
12
. In the signal processing section
12
, a signal processing is carried out in parallel according to the instruction generated by the controller
18
by means of the PEs
16
. The processed signal is output from the signal output circuit
17
to the outside of the chip.
In the image input chip shown in
FIG. 1
, thus, the image input section and the signal processing section are formed on the same chip. Therefore, as compared with the case in which the signal processing is carried out with a signal processing chip other than the image input chip, the system size can be reduced and an inexpensive image input system can be implemented.
In the image input system in which the image input chip and the signal processing chip are divided, moreover, it is necessary to drive a comparatively great load capacity attached to a wiring when a signal is to be transmitted from the image input chip to the signal processing chip. For this reason, consumed power has been increased. In the chip shown in
FIG. 1
, however, it is not necessary to consume power for signal transmission between the chips. Consequently, an image input system having low power consumption can be implemented.
However, the conventional example shown in
FIG. 1
has the following problems. More specifically, when the PEs
16
are arranged for each column of the array of pixel
14
, the width in the column direction of the pixel
13
is small, that is, approximately several &mgr;m. Therefore, the circuit scale and the signal processing capability of the PE
16
which can be arranged are limited, resulting in a low signal processing speed. In general, the amount of data to be processed is large in an image processing. Therefore, if the signal processing speed is low, troubles are practically made. Thus, the use of the image input device is restricted.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a processor capable of processing image data at a high speed.
It is another object of the present invention to provide an image input system which can process image data at a high speed and consumes less power.
The present invention provides a processor comprising a plurality of processors, each of the processors including a plurality of processing elements having the same data processing function, each of the processors receiving a control signal, and the plurality of processing elements in the processor carrying out a data processing in parallel in response to the control signal, a controller for giving the control signal to the processors, and a plurality of data transfer lines provided for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other.
The present invention provides an image input system comprising a solid image sensing section including an array of pixels in which a plurality of pixels are arranged in a matrix and a data read-out circuit for reading a signal from the pixel in the array of pixel and outputting pixel data, a signal processing section including a plurality of processors, the signal processing section being provided adjacently to the solid image sensing section, each of the processors including a plurality of processing elements having the same function, each of the processors receiving the pixel data read from the solid image sensing section and a control signal, the processing elements in each of the processors carrying out a data processing using the pixel data in parallel in response to the control signal, and a plurality of first data transfer lines for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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patent: 5949483 (1999-09-01), Fossum et al.
patent: 6166367 (2000-10-01), Cho
patent: 6303923 (2001-10-01), Wadsworth et al.
patent: 2001/0012070 (2001-08-01), Enod et al.
Jeffrey C. Gealow, et al., “System Design For Pixel-Parallel Image Processing”, IEEE Transactions On Very Larg Scale Integration (VLSI) Systems, vol. 4, No. 1, Mar. 1996, pp. 32-41.
Jeffrey C. Gealow, et al., “A Pixel-Parallel Image Processor Using Logic Pitch-Matched To Dynamic Memory”, IEEE Journal Of Solid-State Circuits, vol. 34, No. 6, Jun. 1999, pp. 831-839.
Jeffrey C. Gealow, “an Integrated Computing Structure For Pixel-Parallel Image Processing”, Massachusetts Institute Of Technology, Jun. 1997, pp. 1-129.
Sodini Charles G.
Yamashita Hirofumi
Allen Stephone
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Spears Eric
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