Phase lock loop (PLL) apparatus and method

Details Phase lock loop (PLL) apparatus and method Phase lock loop (PLL) apparatus and method

2000-11-13

2002-07-23

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C331S017000, C331S040000, C331S057000

Reexamination Certificate

active

06424192

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a radio frequency (RF) communications system, and in particular to a phase lock loop (PLL) including a multi-phase sampling fractional-N prescaler and CMOS voltage controlled oscillator for the PLL.
2. Background of the Related Art
Presently, a radio frequency (RF) communication system has a variety of applications including PCS communication, IMT systems such as IMT 2000, and WLL. As such, a single chip CMOS integration of the system has been pursued to reduce the cost, size and power consumption. Accordingly, a low phase noise integrated voltage controlled oscillator (VCO) for RF communication applications has been broadly researched. However, current VCO CMOS technology can support reliable operation only up to a frequency of approximately 1.0 GHz in terms of speed and noise. As the frequency f
0
of local oscillator clock signals LO+LO−increases over one GHz, a CMOS VCO cannot be implemented.
To get the low phase noise sufficient for commercial applications such as PCS, however, an LC-resonant oscillator is used because of better phase noise performance than a CMOS ring-oscillator type VCO. As described above, the related art VCO has various disadvantages. For a CMOS single chip integration of an RF receiver or communication system, on-chip implementation of a spiral inductor has not been achieved with yields sufficient for mass-production manufacturing because the Q-factor of the integrated spiral inductor should be high enough for VCO oscillation. Manufacturing yield for the high Q-factor is difficult to achieve for the on-chip spiral inductor because of distributed lossy resistance of the substrate.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
A further object of the present invention is to fabricate a RF communications system including a PLL on a single CMOS chip.
Another object of the present invention is to increase the frequency range of a PLL.
Another object of the present invention is to reduce the noise of a PLL.
Another object of the present invention is to increase the performance of PLL.
Another object of the present invention is to provide a CMOS VCO for a PLL that can minimize phase-noise of a CMOS ring oscillator.
Another object of the present invention is provide a VCO that can output a large amplitude signal with a rise-fall time reduced or minimized.
Another object of the present invention is to reduce or minimize supplying noise effects of the VCO.
Another object of the present invention is to provide a prescaler for the PLL having increased bandwidth and spectral performance.
Another object of the present invention is to provide a fractional-N prescaler architecture that eliminates a fractional-spur problem.
To achieve the above advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a circuit that includes a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency and a prescaler coupled to said clock generator for receiving the plurality of first clock signals to generate a divided clock second clock signal.
To further achieve the above advantages in a whole or in parts, there is provided a receiver for a radio frequency (RF) communications system that includes an RF section coupled to receive an input RF signal, a baseband section coupled to the RF section to receive corresponding baseband signals from the RF section, a phase lock loop (PLL) coupled to the RF section, wherein the phase lock loop includes a phase detector that receives a reference frequency signal, a charge pump and loop filter coupled to the phase detector, a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency and a prescaler coupled to said clock generator for receiving the plurality of first clock signals to generate a divided clock second clock signal, and a tuning circuit that outputs a control signal to the baseband section.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 4755774 (1988-07-01), Heck
patent: 5012142 (1991-04-01), Sonntag
patent: 5175729 (1992-12-01), Borras et al.
patent: 5179303 (1993-01-01), Searles et al.
patent: 5180994 (1993-01-01), Martin et al.
patent: 5408201 (1995-04-01), Uriya
patent: 5418815 (1995-05-01), Ishikawa et al.
patent: 5438591 (1995-08-01), Oie et al.
patent: 5448772 (1995-09-01), Grandfield
patent: 5507025 (1996-04-01), Rodeffer
patent: 5555182 (1996-09-01), Galm
patent: 5584062 (1996-12-01), Meador et al.
patent: 5614868 (1997-03-01), Nielson
patent: 5734970 (1998-03-01), Saito
patent: 5761617 (1998-06-01), Yonekura et al.
patent: 5794119 (1998-08-01), Evans et al.
patent: 5861773 (1999-01-01), Meyer
patent: 5872810 (1999-02-01), Phillips et al.
patent: 5880613 (1999-03-01), Ishihara
patent: 5889437 (1999-03-01), Lee
patent: 5894592 (1999-04-01), Brueske et al.
patent: 5950119 (1999-09-01), McGeehan et al.
patent: 5963855 (1999-10-01), Lussenhop et al.
patent: 6084905 (2000-07-01), Ishifuji et al.
patent: 6097768 (2000-08-01), Janesch et al.
patent: 6194947 (2001-02-01), Lee et al.

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