Synchronous double data rate DRAM

Details Synchronous double data rate DRAM Synchronous double data rate DRAM

2000-12-15

2002-09-03

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189011

Reexamination Certificate

active

06445642

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous double data rate DRAM (DDR-SDRM) and, more particularly to an improvement of the read/write performance of a DDR-SDRM.
2. Description of the Related Art
In a DDR-SDRM (which may be referred to as simply SDRAM, hereinafter), the read/write operation is controlled by a system clock signal CLK supplied as an external clock signal, whereas read/write data are transferred between the SDRAM and the external circuit in synchrony with a data strobe signal DQS. The data strobe signal DQS occurs with a specified phase delay with respect to the clock pulse in the system clock signal CLK. The pulses in both the system clock signal CLK and the data strobe signal DQS have the same pulse duration.
More specifically, the read/write operation is controlled in synchrony with the system clock signal CLK whereas the latch of the input write data is controlled with the data strobe signal DQS supplied form outside the DRAM. The relationship between the system clock signal CLK and the data strobe signal DQS is specified by the JEDEC standard. For example, it is prescribed that the phase difference between the system clock signal CLK and the data strobe signal DQS reside between 75% and 125% of the clock period Tck of the system clock signal CLK.
FIG. 1
shows signal flows in a conventional DDR-SDRM during a write operation, the DDR-SDRM including a data write section
10
, data read section
30
and an address processing section not shown in the figure. The system clock signal CLK is supplied through a clock buffer
11
to a command decoder
12
, a write timing generator
13
and a second-stage data latch (latch section)
18
, whereas the data strobe signal DQS is supplied to a first-stage data latch (latch section)
17
. In the DDR-SDRM, a read/write operation is controlled in synchrony with the system clock signal CLK whereas the latch of the input data DQ at the first-stage latch
17
is controlled by the data strobe signal DQS.
FIG. 2
shows a timing chart of the signals in the DDR-SDRM of
FIG. 1. A
write cycle is started with a first pulse P
1
of the system clock signal CLK. The write data DQ and the data strobe signal DQS are supplied from outside the SDRM. First write data DQ
0
is latched at time t
0
by responding to the rising edge of the data strobe signal DQS and second write data DQ
1
is latched at time t
1
by the falling edge of the same data strobe signal DQS in the first-stage latch
17
. The second-stage latch
18
latches both the write data DQ
0
and DQ
1
at time t
2
by responding to the rising edge of the system clock signal CLK to deliver both the write data DQ
0
and DQ
1
to the write buffer (write buffer section)
14
. The I/O lines
19
includes a first pair of complementary I/O lines disposed for bit lines having even serial numbers, and a second pair of complementary I/O lines disposed for bit line pairs having odd serial numbers.
The write buffer
14
delivers a differential voltage signal corresponding to the write data latched at the rising edge of the data strobe signal DQS through one of the pairs of complementary I/O lines
19
, and delivers at the same time a differential voltage signal corresponding to the write data latched at the falling edge of the data strobe signal DQS through the other of the pairs of the I/O lines
19
. The former I/O lines are called herein I/O lines (R) whereas the latter I/O lines are called herein I/O lines (F). The potential difference of the differential voltage signal is 2.2 volts in this example. The write operation ends at time t
3
b
at which the I/O lines
19
are subjected to balancing or equalizing the pair of I/O lines
19
.
A read cycle is started at time t
4
with a fourth pulse P
4
in the system clock signal CLK, and a read amplifier
15
delivers a pair of differential voltage signals through the I/O lines
19
, the differential voltage assuming 0.2 volts in the read operation. The read data DQ
2
and DQ
3
and the data strobe signal DQS are fed to outside from the DDR-SDRM. The data strobe signal DOS is generated in the DDR-SDRM during the read operation in synchrony with the system clock signal CLK. The time interval between t
3
b
at which the write operation is finished and t
4
at which the read operation is started is used as a balancing time interval, during which the I/O lines
19
are isolated from the bit lines of the memory cell plate
16
.
In the above operation, the DDR-SDRM operates for equalizing the pair of I/O lines
19
, which had a potential difference of 2.2 volts in the write operation, during the balancing time interval for preparing the next read operation. However, the time length may be too short for a safe operation, especially if the read data in the succeeding read operation is opposite to the write data supplied in the write operation.
Assuming that the clock period Tck of the system clock signal CLK is 6.5 ns, and coupling operation for coupling the I/O lines and the bit lines together consumes 4 ns, then the available time length for the balancing of the I/O lines is equal to:
6.5−4=2.5 ns.
In this case, the available balancing time interval is too short to assure a safe isolation of the I/O lines from the bit lines.
SUMMARY OF THE INVENTION
In view of the above problem in the conventional technique, it is an object of the present invention to provide a DDR-SDRM, which is capable of solving the above problem and operates at a higher speed and with a higher reliability.
The present invention provides a DDR-SDRM including a memory cell array including a plurality of memory cells, an address signal processing section for receiving and processing an address signal for specifying an address of one of the memory cells, the address signal processing section operating in synchrony with a system clock signal, a data write section for receiving write data and writing the write data into the one of the memory cells in a write cycle, and a data read section for responding to the system clock signal to read data from the one of the memory cells in a read cycle to deliver read data, the data write section operating based on a data strobe signal transferred in synchrony with the write data to receive the write data from outside the DDR-SDRM and deliver the write data through I/O lines to the one of the memory cells.
In accordance with the present invention, the write operation conducted based on the data strobe signal by the data write section assures a sufficient balancing time interval for balancing the I/O lines, whereby a safe read data can be obtained during a succeeding read operation.


REFERENCES:
patent: 6147926 (2000-11-01), Park

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