Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-20
2002-07-09
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185040, C365S185110, C365S185280
Reexamination Certificate
active
06418061
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and particularly relates to a non-volatile semiconductor memory device which permits reading of data during a process of rewriting of data.
2. Description of the Related Art
In recent years, many different types of flash EEPROMs (hereinafter referred to as flash memories) have been launched in the market as main items of a product line covering non-volatile semiconductor memory devices which permit electrical writing and erasing of data.
In general, a flash memory needs a longer time period to complete a data rewriting operation than does a DRAM (dynamic random access memory) or an SRAM (static random access memory). Also, a flash memory does not allow a data reading operation to be performed while a data rewriting operation is being performed.
In order to obviate these inconveniences, a flash memory of a dual-operation type has been developed. This type of flash memory has a plurality of banks of memory-cell arrays for data storage, and allows a data reed operation to be performed in one bank while a data rewrite operation is performed in another bank. Here, the term “bank” refers to one block or a group of two or more blocks, which operates as one data processing unit.
FIG. 1
is a block diagram showing a configuration of a dual-operation-type flash memory.
A flash memory
10
of
FIG. 1
includes a bank
1
and a bank
2
. The bank
1
includes a memory-cell array
11
, an X decoder
12
, a Y decoder
13
, and a data-read circuit
14
. The bank
2
includes a memory-cell array
21
, an X decoder
22
, a Y decoder
23
, and a data-read circuit
24
. The flash memory
10
further includes a data-write circuit
31
, a data-erase circuit
32
, a control circuit
33
, an address buffer
34
, an address generator
35
, an output circuit
36
, an address-input terminal
41
, a data-input/output terminal
42
, and a RD/BY terminal
43
.
As can be seen from
FIG. 1
, the flash memory
10
has the two sets of memory-cell arrays, each of which is provided with the X decoder and the Y decoder for selecting memory cells as well as the data-read circuit for reading data from the selected memory cells. On the other hand, only one set of the data-write circuit
31
and the data-erase circuit
32
is provided and shared by the banks
1
and
2
because these circuits occupy a large chip area. Here, the data-write circuit
31
is used for writing data, and the data-erase circuit
32
is used for erasing data.
With this configuration, the flash memory
10
cannot perform a rewrite operation in the two banks at the same time. It is possible, however, to read data from one bank while rewriting data in the other bank. The term “dual operation” is used for describing such an operation in which a data is read from one bank while data is rewritten in the other bank.
In what follows, a description will be given with regard to the dual operation.
When a command for writing or erasing data in the bank
1
is entered, the address buffer
34
stores therein an address at which data is written or erased. The data-write circuit
31
uses the data-write circuit
31
or the data-erase circuit
32
to write or erase data at the specified address. In the case of data-write operation, data to be written is entered from the data-input/output terminal
42
, and is supplied to the date-write circuit
31
.
While the data-write or data-erase operation as described above is underway, a read address is supplied to the address-input terminal
41
. In response, the control circuit
33
controls the address buffer
34
to supply the read address to the bank
2
rather than supplying it to the bank
1
. The bank
2
has its own set of the X decoder
22
, the Y decoder
23
, and the data-read circuit
24
separate from that of the bank
1
, so that data can be read from memory cells of the memory-cell array
21
.
The read address entered during an ongoing data-write or data-erase operation needs to be an address that is included in a bank different from the one that is undergoing the data-write or data-erase operation. Data read from the memory cells is output from the data-input/output terminal
42
.
The flash memory
10
has the RD/BY terminal
43
for outputting a signal indicative of whether a date-write or data-erase operation is underway. When a signal output at the RD/BY terminal
43
is HIGH, for example, it generally indicates that no data-write or data-erase operation is underway in the flash memory
10
, and that data can be read. When a signal output at the RD/BY terminal
43
is LOW, on the other hand, it generally indicates that there is an ongoing data-write or data-erase operation in the flash memory
10
, and that data cannot be read.
In the flash memory
10
of FIG. l, the signal output at the RD/BY terminal
43
is LOW when one of the banks is undergoing a data-write or data-erase operation. A data-read operation directed to the other bank, however, is not prohibited.
Data erasure in a flash memory is performed block by block, and the block used as a unit of erasure is generally referred to as a sector. In a flash memory of a dual-operation type as shown in
FIG. 1
, when a plurality of sectors are to be erased, these sectors may exist in more than one bank.
Data erasure is successively performed sector by sector. The problem is that it is impossible to detect, in realtime, a timing at which a data-erase operation is switched from one bank to the other. That is, it is impossible to detect, from outside the flash memory
10
, which one of the banks is ready to perform a data-read operation. This is because the RD/BY terminal
43
outputs a LOW signal when either one of the banks is undergoing a data-write or data-read operation, and there is no way to ascertain which one of the banks is undergoing the data-write or data-read operation.
Accordingly, there is a need for a non-volatile semiconductor memory device which allows a data-read operation to be performed concurrently with a data-write or data-erase operation, and allows validity of read data to be checked from outside the semiconductor memory device.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a non-volatile semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a non-volatile semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a non-volatile semiconductor memory device including a plurality of memory areas, a control unit which performs a data-write or data-erase operation with respect to one of the memory areas, an address-detection unit which detects an address that indicates the one of the memory areas having the data-write or data-erase operation performed therein, and supplies information indicative of the address, and at least one output terminal which supplies the information to an exterior of the device.
Further, the invention provides a non-volatile semiconductor memory device including three or more memory-cell blocks, a control unit which organizes the memory-cell blocks into a plurality of groups, and controls the memory-cell blocks in each of the plurality of groups to operate as one unit separately from the memory-cell blocks of other groups, a data-write/erase unit which writes or erases dat
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Ho Hoai V.
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