Method for forming inner capacitor of semiconductor devices...

Details Method for forming inner capacitor of semiconductor devices... Method for forming inner capacitor of semiconductor devices...

2001-08-13

2002-07-23

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S239000, C438S514000, C438S513000

Reexamination Certificate

active

06423610

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for forming a semiconductor device and, more particularly, to a method for forming an inner capacitor of the semiconductor device.
DESCRIPTION OF THE PRIOR ART
FIG. 1
is a cross-sectional view illustrating a conventional inner capacitor in a semiconductor device. As shown in
FIG. 1
, after forming field oxide layers
11
, source/drain regions
12
, word lines
13
and bit lines
16
in and on a semiconductor substrate
10
, a BPSG (Borophosphosilicate Glass) layer
18
, a SiH
4
-oxide layer
20
and a nitride layer
21
are deposited on the resulting structure. A planarization process is applied to the BPSG layer
18
with a flow and CMP (Chemical Mechanical Polishing) processes. Typically, the nitride layer
21
is employed as an etching stopper and the SiH
4
-oxide layer
20
is employed to prevent the bowing phenomenon generated in sidewalls of a contact hole. In
FIG. 1
, the reference numerals
14
,
15
and
17
denote sidewall spacers of the word lines, a BPSG layer and sidewall spacers of the bit lines, respectively.
Subsequently, after forming contact holes for charge storage electrodes using masking and etching processes, a clearing process is carried out and polysilicon contact plugs
19
are formed within the contact holes. Typically, contact plugs for the bit lines are defined simultaneously with the polysilicon contact plugs for charge storage electrodes.
Next, a PSG (phosphosilicate glass) layer
22
, as a sacrifice oxide layer, is deposited on the resulting structure and the PSG layer
22
is selectively etched in order to expose the polysilicon contact plugs
19
. A polysilicon layer
23
is formed in the contact holes for charge storage electrodes. The single polysilicon layer
23
is divided into a plurality of charge storage electrodes by the CMP process and a relatively wide surface area of charge storage electrodes is provided by the removal of the remaining PSG layer
22
.
In the conventional method for forming the inner capacitor, the PSG layer
22
used as a sacrifice oxide layer is formed in the APCVD (Atmospheric Pressure Chemical Vapor Deposition) equipment having an injector
200
, which is in the form of a bar, as shown in FIG.
2
. The injector
200
has
49
injecting holes
201
which are arranged in a straight line. Since the PSG layer
22
is deposited on the semiconductor substrate mounted on a moving belt by the typical two-pass process while a source gas flows from the injecting holes
201
, there are some areas
301
vulnerable to the thickness uniformity of the PSG layer
22
as shown in FIG.
3
. In
FIG. 3
, the reference numeral
300
denotes a uniform thickness area. In the case where the PSG layer
22
is deposited at a thickness of approximately 11000 Å, the PSG layer
22
has a non-uniformity of about 5%.
FIG. 4
is a schematic layout showing a charge storage electrode contact and a bit line contact, in which a charge storage electrode contact area
401
, a bit line contact area
402
and a charge storage electrode area
403
are shown. When the PSG layer
22
is etched to expose the polysilicon layer
23
for the charge storage electrodes, the nitride layer
21
and the BPSG layer
18
may be etched in the area
301
because of the non-uniformity of thickness of the PSG layer
22
. Accordingly, this loss of the nitride layer
21
and the BPSG layer
18
causes an electrical interconnection (A) between the polysilicon layer
23
for the charge storage electrode and a bit line contact plug.
The loss of the BPSG layer
18
is caused by the loss of the nitride layer
21
and the SiH
4
-oxide layer
20
. The SiH
4
-oxide layer
20
is formed on the BPSG layer
18
at a thickness of approximately 500-2000 Å in order to prevent the bowing phenomenon in sidewalls of the contact holes, because the SiH
4
-oxide layer
20
is hardly etched by a clearing solution that is applied to the contact holes. Typically, since the SiH
4
-oxide layer
20
is formed in a bulk layer by the PECVD (Plasma Enhanced CVD) processing chamber, the quality of the layer is not rigid and then the SiH
4
-oxide layer
20
may be lost with a loss of the upper layer.
As stated above, the method for forming the conventional inner capacitor has a disadvantage in that the loss of the BPSG layer, the nitride layer and the SiH
4
-oxide layer under the sacrifice oxide layer (PSG) layer may occur based on the non-uniformity of thickness of the PSG layer thereon. Accordingly, this loss may cause a short between adjacent metal layers with a resulting failure of the semiconductor device.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for improving the reliability of the semiconductor fabricating process which uses a sacrifice oxide layer.
It is another object of the present invention to provide a method for preventing short circuiting of a charge storage electrode in a semiconductor memory device.
In accordance with an aspect of the present invention, there is provided a method for forming a charge storage electrode in a semiconductor device, the method comprising the steps of forming an interlayer insulation layer over a semiconductor substrate, wherein a plurality of layers to form semiconductor transistors are formed on the semiconductor substrate; forming a SACVD oxide layer on the interlayer insulation layer; forming contact holes for charge storage electrodes and bit lines by selectively etching the SACVD oxide layer and the interlayer insulation layer; forming contact plugs in the contact holes, thereby forming a resulting structure; forming a SACVD sacrifice oxide layer on the resulting structure; selectively etching the SACVD sacrifice oxide layer and exposing top surfaces of the contact plugs; forming a conducting layer electrically connected to the contact plugs; separating the conducting layer into a plurality of charge storage electrodes; and removing the SACVD sacrifice oxide layer.


REFERENCES:
patent: 6037220 (2000-03-01), Chien et al.
patent: 6174808 (2001-01-01), Jang et al.

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