Power consumption reduction method, power consumption...

Details Power consumption reduction method, power consumption... Power consumption reduction method, power consumption...

2000-09-28

2002-08-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S544000

Reexamination Certificate

active

06429704

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a power consumption reduction method of reducing the power consumption of an electronic circuit operating on the basis of a clock signal, and a circuit thereof, and in particular, to a power consumption reduction method of reducing the power consumption at the time of power-on, and a circuit thereof.
2. Description of the Related Art
In hard disk drive (HDD) apparatuses, further increase of recording density has been attempted and increase of storage capacity has been attempted. By attempting the increase of storage capacity, smaller HDD apparatuses such as one-inch HDD apparatuses have been developed. The one-inch HDD apparatuses are used in hand-held information devices such as so-called notebook-sized personal computers, PDAs (Personal Digital Assistance), and digital cameras. The reduction of power consumption is required of these hand-held information devices so as to elongate battery-operating time. For this reason, the reduction of power consumption is also required of HDD apparatuses.
FIG. 8
is a diagram showing the schematic configuration of a control circuit in a conventional HDD apparatus. As shown in
FIG. 8
, a control circuit
1
comprises a plurality of ICs (Integrated Circuits)
11
,
12
, . . . ,
13
. The ICs
11
,
12
, . . . ,
13
are connected to each other via a bus
14
. These ICs
11
,
12
, . . . ,
13
are configured with being classified into respective functions such as an HDC (Hard Disk Controller), MPU (Micro Processing Unit), memory, drivers, and an HI (Host Interface).
In addition, a control circuit
1
comprises a power consumption reduction circuit
10
connected to each of ICs
11
,
12
, . . . ,
13
. A clock signal generator
2
and a reset IC
3
are connected to the power consumption reduction circuit
10
. The clock signal generator
2
and reset IC
3
are provided out of the control circuit
1
. The clock signal generator
2
outputs a clock signal having a predetermined frequency. The reset IC
3
outputs a power-on-reset signal at the time of power-on.
The power consumption reduction circuit
10
selects ICs, which should operate, from among ICs
11
,
12
, . . . ,
13
. The clock signal is outputted to the ICs selected by the power consumption reduction circuit
10
, and is not outputted to ICs not selected by the power consumption reduction circuit
10
. For this reason, the ICs not selected are made to be stopped. In this manner, since it is possible to output the clock signal only to the ICs that should operate, it is possible to reduce the power consumption of the HDD apparatus.
Problems to be Solved by the Invention
Nevertheless, in a conventional power consumption reduction method and a circuit thereof, since each IC is initialized at the time of power-on, it is necessary to output the clock signal to all the ICs. Therefore, the conventional method and circuit thereof have such a problem that it is not possible to reduce the power consumption at the time of power-on.
The present invention is intended to solve such a problem, and an object of the present invention is to provide a power consumption reduction method, a power consumption reduction circuit, a control circuit, and a hard disk drive apparatus that can reduce the power consumption at the time of power-on.
SUMMARY OF THE INVENTION
A power consumption reduction method according to the present invention is-a power consumption reduction method of outputting a clock signal to at least one electronic circuit and reducing power consumed by the at least one electronic circuit, and is characterized in that the method comprises the steps of monitoring a power-on-reset signal at the time of power-on, and outputting the clock signal, having a frequency lower than a frequency at the time of the at least one electronic circuit operating, to the at least one electronic circuit until this power-on-reset signal is negated.
In addition, a power consumption reduction circuit according to the present invention is characterized in that the circuit has a clock signal input terminal for inputting a clock signal, a power-on-reset signal input terminal for inputting a power-on-reset signal, and a clock signal output terminal for outputting the clock signal, and downconverts a frequency of the clock signal inputted through the clock signal input terminal and outputs the clock signal through the clock signal output terminal until the power-on-reset signal inputted through the power-on-reset signal input terminal is negated.
Furthermore, a control circuit according to the present invention is characterized in that the control circuit comprises at least one electronic circuit operating on the basis of a clock signal, and a power consumption reduction circuit having a clock signal input terminal for inputting the clock signal, a power-on-reset signal input terminal for inputting a power-on-reset signal, and a plurality of clock signal output terminals, each of which is connected to each of the at least one electronic circuit, for outputting the clock signal, and the power consumption reduction circuit downconverts a frequency of the clock signal, inputted through the clock signal input terminal, and outputs the clock signal through the clock signal output terminal at the time of power-on until a power-on-reset signal, which is inputted through the power-on-reset signal input terminal, is negated.
In addition, a hard disk drive apparatus according to the present invention is a hard disk drive apparatus that moves a magnetic head to a recording surface of a rotating magnetic disk and performs record/playback of data on the recording surface of the magnetic disk by this magnetic head, the hard disk drive apparatus which is characterized in that the hard disk drive apparatus comprises at least one electronic circuit operating on the basis of a clock signal, and a power consumption reduction circuit having a clock signal input terminal for inputting the clock signal, a power-on-reset signal input terminal for inputting a power-on-reset signal, and a plurality of clock signal output terminals, each of which is connected to each of the at least one electronic circuit, for outputting the clock signal, and the power consumption reduction circuit outputs the clock signal through the plurality of clock signal output terminals with downconverting a frequency of the clock signal inputted through the clock signal input terminal at the time of power-on until the power-on-reset signal inputted through the power-on-reset signal input terminal is negated.
PREFERRED EMBODIMENTS
Hereinafter, a power consumption reduction method and a circuit thereof according to the present invention and their preferable embodiments will be described with reference to drawings.
The power consumption reduction method according to the present invention reduces the power consumption of an electronic circuit, operating on the basis of a CK (clock) signal, at the time of power-on. This power consumption reduction method monitors a POR (Power-On Reset) signal at the time of power-on and downconverts a frequency of the CK signal, supplied to the electronic circuit, until this POR signal is negated.
Supposing that there is a plurality of electronic circuits, their entire power consumption A is composed of:
power consumption C without relating to the frequency of the CK signal; and
power consumption f×M×K proportional to the frequency of the CK signal, and is expressed as follows:
A=C+f×M×K
Here,
f: frequency of a CK signal;
M: constant; and
K: operating rate of a plurality of electronic circuits.
Since the CK signal is supplied to all the electronic circuits at the time of power-on, the operating rate K becomes 1. Therefore, by downconverting the frequency f of the CK signal, it is possible to reduce the power consumption of these electronic circuits.
As methods of downconverting the frequency of the CK signal supplied to an electronic circuit, there are a first method of dividing a frequency of an original CK signal, and a

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