Flash based control for field programmable gate array

Details Flash based control for field programmable gate array Flash based control for field programmable gate array

2000-12-21

2002-03-12

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

C365S185050, C365S185100, C365S185180

Reexamination Certificate

active

06356478

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to field programmable gate array (FPGA) integrated circuits. More particularly, the present invention relates to reprogrammable FPGA devices and to flash memory devices for controlling a switching transistor in a reprogrammable FPGA device.
2. The Prior Art
FPGA integrated circuits are known in the art. FPGA devices may be classified in one of two categories. One category of FPGA devices is one-time programmable and uses elements such as antifuses for making programmable connections. The other category of FPGA devices is reprogrammable and uses transistor switches to make programmable connections.
Reprogrammable FPGA devices include some means for storing program information used to control the transistor switches. Non-volatile memory devices such as EPROMs EEPROMS, non-volatile RAM and flash memory devices have all been proposed for or used to store programming information in the class of reprogrammable FPGA applications.
BRIEF DESCRIPTION OF THE INVENTION
A first circuit for controlling a switching transistor in a reprogrammable FPGA device according to the present invention comprises first and second floating gate flash memory transistors. A first floating gate flash memory transistor has a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to a control gate potential node, and a source coupled to an output node. A second floating gate flash memory transistor has a drain electrically coupled to the output node, a floating gate, a control gate coupled to the control gate potential node, and a source coupled to a second voltage potential. The output node is coupled to the gate of a switching transistor.
A second circuit for controlling a switching transistor in a reprogrammable FPGA device according to the present invention comprises first and second floating gate flash memory transistors having a common floating gate. A first floating gate flash memory transistor has a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to a control gate potential node, and a source coupled to an output node. A second floating gate flash memory transistor has a drain electrically coupled to the output node, a floating gate, a control gate coupled to the control gate potential node, and a source coupled to a second voltage potential. The output node is coupled to the gate of a switching transistor.
The circuit is operated by first erasing the first and second floating gate flash memory transistors. To erase the first and second floating gate flash memory transistors, an erase potential is applied between the control gate potential node and both the drain of the first floating gate flash memory transistor and the source of the second floating gate flash memory transistor. After the first and second floating gate flash memory transistors have been erased, the first floating gate flash memory transistor is programmed if the switching transistor is to be turned on and the second floating gate flash memory transistor is programmed if the switching transistor is to be turned off. The first floating gate flash memory transistor is programmed by applying a programming potential between the control gate potential node and the drain of the first floating gate flash memory transistor. The second floating gate flash memory transistor is programmed by applying a programming potential between the control gate potential node and the source of the second floating gate flash memory transistor.


REFERENCES:
patent: 5587603 (1996-12-01), Kowshik
patent: 5740106 (1998-04-01), Nazarian
patent: 6005806 (1999-12-01), Madurawe et al.
patent: 6144580 (2000-11-01), Murray

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