Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-06-20
2002-09-03
Graybill, David E. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C438S129000, C438S599000, C438S618000, C438S666000
Reexamination Certificate
active
06445066
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit packaging. More particularly the invention relates to associating signal traces and ball contacts with multiple power planes on a power layer of an integrated circuit package.
BACKGROUND
Modern integrated circuits typically require a variety of different voltages. For example, some of the components of an integrated circuit may require five volts, while others of the components may require three volts, or some other voltage.
Traditionally, a separate power layer of an integrated circuit package is provided for each of the different voltages required by the integrated circuit. However, this approach is undesirable, as it results in an increased number of layers. These additional layers tend to add cost to the package in terms of both the cost of materials for each package and the cost of the tooling required to fabricate the packages.
Splitting a single power layer into wedge-shaped power planes that carry different voltages has been used in packages that are customized for specific integrated circuits that have only peripheral contacts. These customized packages tend to have materials and tooling costs that are lower in comparison to those of packages with multiple power layers, but tend to cost more than the multiple power layer packages in terms of longer cycle times to develop a customized package for each different integrated circuit, and the cost to provide a greater number of customized packages, rather than a few generic packages that can accommodate many different integrated circuits.
Further, these wedge-shaped power planes are not altogether satisfactory when applied to packages for integrated circuits that have both peripheral contacts and core contacts. When signal routing initiates from deeper within the integrated circuit, the wedge-shaped power planes become very narrow and less effective in electrically isolating the associated signal traces from cross talk and other signal interference.
What is needed, therefore, is an improvement wherein multiple power planes are incorporated on a single layer of an integrated circuit package for integrated circuits that have both peripheral contacts and core contacts.
SUMMARY
The above and other needs are met by a method for assigning signal traces to one of a plurality of power planes on a power layer of an integrated circuit package. The integrated circuit package has an integrated circuit signal contact region, a top routing layer, and a bottom routing layer. The power layer underlies both the top routing layer and the bottom routing layer.
First signal traces on the bottom routing layer are routed from contacts disposed in a core portion of the integrated circuit signal contact region to first ball contacts disposed within a first perimeter of the integrated circuit package. The first perimeter has dimension corresponding to a first distance from the integrated circuit signal contact region.
Second signal traces on the top routing layer are routed from contacts disposed in a peripheral portion of the integrated circuit signal contact region to second ball contacts. The second ball contacts are disposed outside of the first perimeter of the integrated circuit package and within a second perimeter of the integrated circuit package. The second perimeter has dimensions corresponding to a second distance from the integrated circuit signal contact region, where the second distance is greater than the first distance.
The power layer is segmented into the plurality of power planes. At least a first power plane of the plurality of power planes is bounded within the first perimeter. The first power plane is configured to carry a first voltage corresponding to the first signal traces. The first ball contacts are in proximity to the first power plane.
At least a second power plane of the plurality of power planes is bounded between the first perimeter and the second perimeter. The second power plane is configured to carry a second voltage corresponding to the second signal traces. The second ball contacts are in proximity to the second power plane.
Thus, the method as described above produces a package with correct referencing of both the signal traces and the ball contacts that are associated with a given voltage of a given power plane. Assignments are made so that signal nets routed on the lowest layer in the package are assigned to the ball contacts nearest the center of the package. This allows those signal traces on the layer directly above the bottom routing layer to remain referenced to that interior power plane for their entire length. Each subsequent routing layer is assigned to ball contacts in the next nearest region of the power layer, until finally the uppermost routing layer is assigned to ball contacts at the package edge. The power layer is split into rings in such a way that it provides appropriate referencing for the ball contacts in outer portions of the package, without causing interference with unassociated signal traces on the routing layer directly above it. In a preferred embodiment, these rings can then be further split into wedges to form multiple power planes within a single ring on the power layer, in order to match the splits of the power planes adjacent to the signal routing layers.
REFERENCES:
patent: 4551746 (1985-11-01), Gilbert et al.
patent: 6396137 (2002-05-01), Klughart
patent: 2002/0066951 (2000-12-01), Li et al.
Graybill David E.
LSI Logic Corporation
Luedeka Neely & Graham
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