Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-10-10
2002-04-16
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S090000, C345S092000, C327S333000, C326S081000
Reexamination Certificate
active
06373460
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a matrix-type image display device wherein pixels are arranged in a matrix form on a substrate, and particularly relates to improvements of a driving circuit for display driving each pixel in such matrix-type image display device.
BACKGROUND OF THE INVENTION
Conventionally, image display devices wherein a liquid crystal element, an EL (electro luminescent) element, and an LED (light emitting diode) element, etc., are arranged in a matrix form has been used. Such a matrix-type image display device will be explained below through an example of a liquid crystal display device.
FIG. 11
is a front view showing a schematic structure of a generally used liquid crystal display device
1
. As shown in
FIG. 11
, the liquid crystal display device
1
is mainly composed of a pixel array ARY, a scanning signal line driving circuit gd, a data signal line driving circuit sd and a control circuit
2
.
On the pixel array ARY, a plurality of pixels PIX are formed. The scanning signal line driving circuit sd and the data signal line driving circuit sd are provided for display driving the pixels PIX. The control circuit
2
is provided for controlling the driving of these signal line driving circuits gd and sd.
On the pixel array ARY, a plurality of scanning signal lines GL
j
(j=1, 2, . . . , n) and a plurality of data signal lines SL
i
(i=1, 2, . . . , m) are formed so as to cross at a right angle. Then, in a region surrounded by the adjoining two scanning signal lines GL
j
and GL
j+1
and two data signal lines SL
j
and SL
j+1
, the pixel PIX is formed. As described, the pixels PIX are formed in a matrix form on the pixel array ARY.
The data signal line driving circuit sd samples and if necessary amplifies the image signal DAT as input, and outputs it to each data signal line SL
i
. This sampling is carried out in sync with the timing signal such as a clock signal CKS, etc., from the control circuit
2
. The scanning signal line driving circuit gd sequentially selects the scanning signal lines GL
j
and controls the opening/closing of the switching element (to be described later) provided in the pixel PIX. This control is performed in sync with the timing signal such as a clock signal CKG, GPS, etc., from the control circuit
2
.
By the described operations of the circuits sd and gd, the image signal (data) DAT is output to the data signal line SL
i
to be written in each pixel PIX. Then, until the next scanning timing, the image data DAT is held in each pixel PIX to carry out a display output.
As a system of outputting an image data DAT to each data signal line SL
i
by the data signal line driving circuit sd, a dot sequential driving system and a line sequential driving system have been known. In the dot sequential driving system, the image data DAT are sequentially output to a pixel of a line selected by the scanning signal line GL
j
. In the line sequential driving system, image data DAT are output to pixels on the line as selected at once. An example of the data signal line driving circuit of the dot sequential driving system of a simple circuit structure will be explained with reference to FIG.
12
.
FIG. 12
is a block diagram showing an electric structure of a data signal line driving circuit sd of the dot sequential driving system as a typical conventional example. As shown in the figure, an analog switch asw
i
is formed along each data signal line SL
i
. When the analog switch asw
i
conducts, the image data DAT is sampled to be output to each data signal line SL
i
. In order to control these analog switches asw
i
, scanning circuits srs
i
(i=1, 2, . . . , m) and buffers bufs
i
respectively corresponding to analog switches asw
i
are formed.
The scanning circuits srs
i
are mutually cascade-connected. To each scanning circuit srs
i
, a common clock signal CKS is input. To the leading end of the scanning circuit srs
1
, a start pulse SPS prepared based on a horizontal scanning signal is applied.
When the start pulse SPS is applied to the scanning circuit srs
1
, a sampling pulse is output from each scanning circuit srs
i
. The output of the sampling pulse in each scanning circuit srs
i
is sequentially carried out from the scanning circuit srs
1
of the starting end. The sampling pulse is held and amplified in the buffer bufs
i
, and inverses when necessary to be applied to each analog switch asw
i
.
The scanning signal line driving circuit gd shown in
FIG. 11
, for example, has a structure of FIG.
13
. As shown in the figure, the scanning signal line driving circuit gd includes scanning circuits srg
k
(K=1, 2, . . . , n+1) having the same arrangement as the aforementioned scanning circuit srs
i
, and two kinds of AND circuits and
1
j
and and
2
j
, and a buffer bufg
j
respectively corresponding to the scanning signal lines GL
i
.
Each scanning circuit srg
k
is cascade-connected to the scanning circuit srs
i
. Upon inputting the start pulse SPG prepared based on a vertical sync signal to the leading end scanning circuit srg
1
, the start pulse SPG responds to the clock signal CKG prepared based on the horizontal scanning signal. The start pulses SPG are sequentially output to the scanning circuits srg
2
, srg
3
, . . . in the post stage.
The respective outputs from the adjoining scanning circuits srg
j
and srg
j+1
are computed in an AND circuit and
1
j
. Thereafter, the output from the AND circuit and
1
j
is computed with the clock signal GPS in the AND circuit and
2
j
to be input respectively to the buffer bufg
j
.
In response to the clock signal CKG, each scanning circuit srg
k
outputs the start pulse SPG with a lag of a half period from the srg
k−1
in the post stage. Namely, the pulse to be output from the scanning circuit srg
j
rises at a timing of a rise of the clock signal CKG and is held for one period until the next rise timing. In contrast, the scanning circuit srg
j+1
in the next stage outputs a pulse for one period from a timing of a fall of the clock signal CKG. Namely, the pulse having a time difference of a half period between the adjoining scanning circuits srg
j
and srg
j+1
, is input to the AND circuit and
1
j
. Therefore, from the AND circuit and
1
j
, the pulse of a length of a ½ period of the clock signal CKG is output to the AND circuit and
2
j
.
The speed of the clock signal GPS is, for example, twice as high as that of the clock signal CKG. Therefore, the pulse to be output from the AND circuit and
2
j
is shorter than a ½ period of the clock signal CKG, thereby preventing a generation of a period in which pulses are overlapped between the adjoining AND circuits and
2
j
and and
2
j+1
. The output from the AND circuit and
2
j
is amplified in the buffer bufg
j
and inverses if necessary to be output to each scanning signal line GL
j
.
Here, respective driving voltages for the signal line driving circuits gd and sd will be considered. The driving voltage for the data signal line driving circuit sd is selected to satisfy the conditions of: (a) the scanning circuit srs
i
can be driven at a frequency as desired, and (b) the image data DAT of both positive and negative polarities can be output to the data signal line SL
i
. Specifically, the desirable frequency is around 25.2 MHz in the case of the VGA (Video Graphical Array) display in the case where the scanning signal line driving circuits gd are not aligned in parallel or the sampling is not carried out simultaneously. In general, the driving voltage is determined based on a request from the analog switch asw
i
rather than a request from the scanning circuit srs
i
.
For example, when the liquid crystal driving voltage is +5V, and the voltage of the counter electrode is 0 V, the level of the image signal at the data signal line SL
i
is in a range of from −5 to +5V, and the driving voltage of the data signal line driving circuit sd is in a range of from −5 to +5 V.
In contrast, in the scanning signal line driving circuit gd, th
Kubota Yasushi
Sakai Tamotsu
Shiraki Ichiro
Awad Amr
Nixon & Vanderhye P.C.
Saras Steven
LandOfFree
Matrix-type image display device having level shifters does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Matrix-type image display device having level shifters, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Matrix-type image display device having level shifters will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2885313