Power factor correction circuit

Details Power factor correction circuit Power factor correction circuit

2000-10-30

2002-09-10

Berhane, Adolf Deneke (Department: 2838)

Electricity: power supply or regulation systems

For reactive power control

Using converter

C363S089000

Reexamination Certificate

active

06448744

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to processing systems and specifically to a power factor correction circuit for a processing system.
BACKGROUND OF THE INVENTION
Power factor correction (PFC) circuits are commonly used in desktop computers where a high power factor is required.
FIG. 1
depicts a conventional PFC circuit configuration
10
. The PFC circuit configuration
10
includes a boost stage portion
11
coupled to an isolated DC/DC converter portion
12
. The boost stage portion
11
includes an AC line voltage input
13
coupled to a rectifier bridge
14
wherein the rectifier bridge
14
is coupled to a first capacitor
16
. The first capacitor
16
is coupled to an inductor
18
wherein the inductor
18
is coupled to two diodes
20
,
22
and a transistor
24
. The transistor
24
is coupled to a pulse width modulator
26
and the diode
20
is coupled to a bulk capacitor
28
.
The isolated DC/DC converter portion
12
includes a pulse width modulator
30
coupled to a transistor
34
wherein the transistor
34
is coupled to a transformer
32
. The transformer
32
is coupled to two diodes
36
,
38
. The two diodes
36
,
38
are coupled to an inductor
42
wherein the inductor
42
is coupled to a capacitor
44
and an output
46
. The output
46
is coupled to an error amplifier
40
wherein the error amplifier
40
is coupled to the pulse width modulator
30
. The boost stage
11
develops a high voltage (i.e. 400V) across the bulk capacitor
28
and the isolated DC/DC converter portion
12
converts the high voltage to a lower voltage (for example, 5V) output.
However, because the conventional PFC circuit configuration
10
implements two stages (boost stage and DC/DC conversion stage) of power conversion, the overall efficiency is reduced. Because each stage of power conversion has a degree of inefficiency, the implementation of two stages of power conversion reduces the overall efficiency of the circuit. For example, if each stage of power conversion maintains an efficiency of 0.9, then the overall efficiency of the circuit is 0.81 (0.9×0.9).
Accordingly, what is needed is an improved PFC circuit that is more efficient than conventional PFC circuits. The circuit should be simple, cost effective and capable of being easily adapted to current technology. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A single stage power factor correction circuit is disclosed. The circuit comprises a first comparator for receiving an output voltage and a reference voltage and for providing a control voltage, a multiplier coupled to the first comparator for receiving the control voltage and an input voltage and then providing a sine wave voltage and a control portion coupled to the multiplier for controlling the sine wave voltage and providing a regulated DC output.
Through the use of the circuit in accordance with the present invention, circuit efficiency is increased and the number of circuitry components is reduced. By reducing the number of circuitry components a significant reduction in manufacturing costs is achieved.


REFERENCES:
patent: 5233509 (1993-08-01), Ghotbi
patent: 5640310 (1997-06-01), Yasumura
patent: 5644214 (1997-07-01), Lee
patent: 5818707 (1998-10-01), Seong et al.
patent: 5847942 (1998-12-01), Bazinet et al.
patent: 5949229 (1999-09-01), Choi et al.
patent: 5969962 (1999-10-01), Gabor
patent: 5973946 (1999-10-01), Yasumura
patent: 6178104 (2001-01-01), Choi

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