Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2000-04-25
2002-09-24
Kim, Robert H. (Department: 2882)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S208100, C250S214100, C257S435000
Reexamination Certificate
active
06455836
ABSTRACT:
BACKGROUND OF THE INVENTION
Digital imaging devices often employ arrays of photo-detectors fabricated within an integrated circuit (IC). For example, a digital camera may employ an IC having an array of PIN diodes, where the P and the N refer to the presence of the normal positive and negative ionic dopants for silicon, and the I represents an intervening layer of intrinsic (undoped) silicon. Arrays of other types of photo-detectors are also possible, and the imaging device might be a scanner for a document or some other type of facsimile machine (e.g., an “office copier”). In any event, it is often the case that the portion of the photo detector array structure that is nearest the exposing to light (i.e., the optical surface upon which an image is focused or registered) is electrically common to each photo-detector in the array, functions as photo current return, and needs to be electrically connected to either ground or perhaps some bias potential. The common connection to all the photo-detectors in the array is accomplished by coating the optical surface of the photo-detector array with a conductive layer that is optically transparent, such as ITO (Indium Tin Oxide). Beneath the coated optical surface are the differentiated structures in the semiconductor material that serve as individual optical sensors at the pixel level, and that are each connected to some form of measurement circuitry through a buffer mechanism, such as a source follower.
Ideally, the signal level associated with each individual pixel sensor would be a function only of the amount of light reaching it. In practice, this is not the case and there is an additional “dark current” whose presence, if not accounted for, degrades the quality of the resulting image. The first step in accounting for dark current is to measure it. Actual measurements of the dark current for each individual pixel are often impractical. For example, to do so might require an actual optical shutter mechanism that is undesirable for various reasons. Fortunately, there is an excellent compromise where certain optical sensors (say, around the periphery) are fabricated as part of the array but are never exposed to light. The dark current of these sensors is measured, averaged and used as an indicator of the dark current for the balance of the array. An optical barrier, such as one of Tungsten (W) as described in the incorporated Specification, can be used for this purpose.
One conventional fabrication technique for an array of the sort that is described above involves the following steps:
(a) Depositing a P layer of hydrogenated amorphous silicon (a-Si:H) upon an underlying layer of intrinsic hydrogenated amorphous silicon;
(b) Patterning the P layer and the underlying intrinsic layer of hydrogenated amorphous silicon;
(c) Depositing and then patterning the layer of conductive ITO; and
(d) Depositing and then patterning the layer of W that serves as the optical barrier.
In the terminology of IC fabrication, there are three masking operations needed to carry out the above steps. Each masking operation requires time and expense expended during production, and each masking operation can contribute additional complexity that may become the occasion for various failure mechanisms.
Thus, it would be desirable if the number of masking operations needed could be reduced. In addition, it will be remembered that the layer of ITO needs to be connected to ground or to a bias potential. It is then further desirable for there to be a way to connect the layer of ITO to ground or a bias potential without incurring a penalty in terms of additional masking operations and/or decreased yield. What to do?
SUMMARY OF THE INVENTION
The number of masking operations needed can be reduced by collecting and rearranging the steps listed above to become:
(A) Depositing a P layer of hydrogenated amorphous silicon (a-Si :H) upon an underlying layer of intrinsic hydrogenated amorphous silicon, and a layer of conductive ITO on top of the P layer;
(B) Patterning all three of the layers deposited in step (A); and
(C) Depositing and then patterning the layer of W that serves as the optical barrier.
The above steps (A)-(C) require only two masking operations. In addition, the W layer can be used to connect the ITO to ground or the bias.
REFERENCES:
patent: 5151385 (1992-09-01), Yamamoto et al.
patent: 6326601 (2001-12-01), Hula et al.
Agilent Technologie,s Inc.
Kim Robert H.
Miller Edward L.
Thomas Courtney
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