Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-10-19
2002-07-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S210000, C327S211000, C327S215000, C327S218000
Reexamination Certificate
active
06417711
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to electronic storage devices, and more particularly, to latch and flip-flop circuits commonly used in digital electronic devices.
Advances in integrated circuit technology and design have led to a rapid increase in integrated circuit performance. A good example of this increase in performance can be seen in microprocessors. Only a few years ago, state-of-the-art microprocessors shipped with personal computers had clock rates of around 60 MHz. Today, personal computers are commonly shipped with microprocessors having clock rates of 600 MHz or more.
FIG. 1
shows a typical delay path within a digital circuit. Such delay paths are commonly used in microprocessors and other digital circuits. A typical delay path includes a first register
101
, a second register
103
and a combinational logic block
102
located therebetween. In the diagram shown, both the first register
101
and the second register
103
are clocked by a common clock signal
105
. For purposes of illustration, both the first register
101
and the second register
103
are assumed to be positive edge triggered master-slave flip-flops.
In operation, and as shown in
FIG. 2
, the first register
101
releases data to the combinational logic
102
at a first positive edge of the clock signal
105
. There is typically a delay
204
, commonly referred to as a clock-to-q delay, before the data actually emerges from the first register
101
. The data emerging from the first register
101
is shown at
209
. The clock-to-q delay
204
typically corresponds to the time required to propagate the data signal through the slave of the master-slave flip-flop, as further described below. Once the data emerges from the first register
101
, the data must propagate through the combinational logic block
102
, and arrive at the data input of the second register
103
at least one setup time
206
before the next positive edge of the clock signal
105
. The arrival of the data at the data input of the second register is shown at
211
. The setup time
206
typically corresponds to the time required to set the state of the master of the master-slave flip-flop, as further described below.
To maximize the performance of the delay path, it is desirable to minimize the clock-to-q delay
204
and the setup time
206
. This leaves the maximum amount of propagation time
205
for the data to travel through the combinational logic block
102
. By reducing the clock-to-q delay
204
and/or the setup time
206
, the clock rate of the clock signal
105
can be increased, thereby increasing the performance of the corresponding digital circuit. Alternatively, a longer delay path can be provided in the combinational logic block
102
, which may help reduce the number of pipeline stages often required in many of today's microprocessors.
FIG. 3
is a schematic diagram of a typical positive edge triggered master-slave flip-flop in accordance with the prior art. The flip-flop includes a master latch
301
and a slave latch
302
, with the output of the master latch
301
coupled to the input of the slave latch
302
. Because the illustrative master-slave flip-flop is positive edge triggered, the master latch
301
is transparent and the slave latch
302
is latched when the clock signal
315
is low, and the master latch
301
is latched and the slave latch
302
is transparent when the clock signal
315
is high.
The master latch
301
includes a pair of looped inverters
305
and
306
forming an inventor loop as shown in FIG.
3
. One side of the looped inverters is coupled to a data output terminal
307
, and the other side of the looped inverters is coupled to the data input terminal
303
of the master-slave flip-flop through a transmission gate
304
. The transmission gate
304
connects the data input terminal
303
of the master-slave flip-flop to the input of the first inverter
305
and the output of the second inverter
306
when the clock signal
315
is low (and thus the complement clock signal
316
is high). In this state, the master latch
301
is transparent, allowing the data input signal
303
to set the state of the cross-coupled inverters
305
and
306
.
The transmission gate
304
disconnects the data input terminal
303
from the input of the first inverter
305
and the output of the second inverter
306
when the clock signal
315
is high (and thus the complement clock signal
316
is low). In this state, the master latch
301
is latched, allowing the looped inverters
305
and
306
to store the state set by the data input signal
303
.
Like the master latch
301
, the slave latch
302
includes a pair of looped inverters
309
and
310
. One side of the looped inverters
309
and
310
is coupled to a data output terminal
311
, and the other side of the looped inverters is coupled to the output terminal
307
of the master latch
301
through a transmission gate
308
. The transmission gate
308
connects the output terminal
307
of the master latch
301
to the input of the first inverter
309
and the output of the second inverter
310
when the clock signal
315
is high (and thus the complement clock signal
316
is low). In this state, the slave latch
302
is transparent, allowing the data output signal
307
of the master latch
301
to set the state of the looped inverters
309
and
310
.
The transmission gate
308
disconnects the output terminal
307
of the master latch
301
from the input of the first inverter
309
and the output of the second inverter
310
when the clock signal
315
is low (and thus the complement clock signal
316
is high). In this state, the slave latch
302
is latched, allowing the looped inverters
309
and
310
to store the state set by the data output signal
307
.
During operation, the clock signal
315
may initially be low and the complement clock signal
316
may be high. At this time, the master latch
301
is transparent, allowing the data input signal
303
to enter the master latch
301
and set the state of the looped inverters
305
and
306
. The slave latch
302
is in a latched state, preventing the output signal
307
of the master latch
301
from reaching the looped inverters
309
and
310
of the slave latch
302
.
The data input signal
303
must be stable for a sufficient period to set the state of the looped inverters
305
and
306
to a desired state before the clock signal
315
rises. As indicated above, this is referred to as the setup time of the master-slave flip-flop. For the master-slave flip-flop shown, the setup time corresponds to about three gate delays, including the delay through the transmission gate
304
, the first inverter
305
and about three or more gate delays to produce a complement data output signal via second inventor
306
as shown in FIG.
3
. When the clock signal
315
rises (and thus the complement clock signal
316
falls), the transmission gate
304
disconnects the data input signal
303
from the pair of looped inverters
305
and
306
. The pair of looped inverters
305
and
306
then maintain or store the data state set during the setup period.
As the clock signal
315
rises, the transmission gate
308
of the slave latch
302
goes transparent, passing the data state stored in the master latch
301
to the output
311
of the master-slave flip-flop. That is, the rising edge of the clock signal
315
opens the transmission gate
308
of the slave latch
302
, which then allows the data state on the output terminal
307
of the master latch
301
to propagate to the output terminal
311
of the slave latch
302
. For the master-slave flip-flop shown, this delay corresponds to the clock-to-q delay. The clock-to q delay is about two gate delays, including the delay through the transmission gate
308
and the first inverter
309
. If a complement output signal
320
is desired, the clock-to-q delay is increased to about three gate delays with the addition of inverter
314
.
SUMMARY OF THE INVENTION
The present invention overcomes many disadvan
Bremer Dennis C.
Cunningham Terry D.
Honeywell Inc.
Nguyen Long
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