Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-01-25
2002-03-26
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S034000
Reexamination Certificate
active
06362674
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the provision of noise immunity for binary signals on an integrated circuit chip.
BACKGROUND OF THE INVENTION
There are many potential sources of noise that can corrupt data being transmitted on a transmission path on an integrated circuit chip. These sources of noise include both on-chip sources and off-chip sources. For instance, phase locked loops (PLLs) tend to be very noisy. Strong drivers, such as data and address bus drivers also create significant noise. For example, an address bus may need to drive the pins of a chip, and therefore would tend to have a strong and, therefore, noisy driver. When all or at least a significant number of bits on an address bus switch states simultaneously, a large burst of very short duration noise is created that could affect and corrupt data on nearby lines on the chip. Accordingly, it is typically a design objective to avoid running transmission paths near high noise devices or zones on the chip. However, sometimes this is impossible.
Further, noisy devices from off-chip also can corrupt data on the chip through electric and/or magnetic coupling.
A noise burst can cause a state change of a binary signal passing through an affected path on the chip, thus corrupting the data. A noise burst that temporarily raises the voltage on an affected transmission path during the transmission of a binary 0 bit on that path can cause the bit to be received at the receiving end as a binary 1. A noise burst that temporarily lowers the voltage on an affected transmission path during the transmission of a binary 1 bit on that path can cause the bit to be received as a binary 0.
A noise burst that raises the voltage on a path enough to cause a binary 0 being transmitted on a noise affected path to temporarily appear as a binary 1 is herein termed a positive noise glitch. Similarly, a noise burst that lowers the voltage on a path enough to cause a binary 1 being transmitted on a noise affected path to temporarily appear as a binary 0 is herein termed a negative noise glitch. It should be clear that a positive glitch generally should not affect the validity of a transmitted binary 1 because raising the voltage on a path during transmission of a binary 1 will still cause it to be received as a binary 1. Likewise, a negative glitch generally should not affect the validity of a transmitted binary 0 because lowering the voltage on a path during transmission of a binary 0 will still cause it to be received as a binary 0.
It is desirable to make digital (i.e., binary) signals on chips immune to such noise.
SUMMARY OF THE INVENTION
The present invention makes binary transmission lines on a chip immune to positive and negative noise glitches. The invention comprises providing two complementary lines rather than a single line for each data transmission path through potentially noisy chip areas. Accordingly, a signal generated in one area of the chip is split and transmitted over two transmission lines to the receiving chip component. The data on one of the two paths is inverted at the beginning of the transmission path or at least prior to entering the noisy area of the chip. At the receiving end, a new type of flip-flop, herein termed a UV flip-flop, receives the two complementary signals at its U and V inputs, respectively.
The UV flip-flop of the present invention operates similar to an SR flip-flop except that there are two memory states rather than one, namely 0-0 at the U and V inputs, respectively, and 1-1 at the U and V inputs, respectively. Accordingly, in the absence of noise, a transmitted binary 1 is received as 1-0 at the U and V inputs, respectively, and a transmitted binary 0 is received as 0-1 at the U and V inputs, respectively. The Q or {overscore (Q)} output of the UV flip-flop is then fed to the receiving circuit component as the received binary bit.
Since the two lines are supposed to be complementary, receipt of a 0-0 at the U and V inputs could only be the result of a negative noise glitch on one or both of the paths. Likewise, receipt of a 1-1 could only be the result of a positive noise glitch on one or both of the paths. However, since 0-0 and 1-1 are both memory states, noise glitches of a duration short enough to occur entirely within the duration of a single binary symbol (1 or 0) will have no effect on the output of the UV flip-flop. Accordingly, the output of the UV flip-flop is noise immune with respect to short duration positive and negative noise glitches.
It can be seen from the discussion above that it is assumed herein that any given noise glitch affects both of the complementary lines simultaneously. However, it should be understood that a noise glitch affecting only one of the lines is still corrected by the present invention. The only problematic situation would be if a negative noise glitch occurred on one of the complementary lines carrying a binary 1 and a positive noise glitch occurred on the other line carrying a binary 0. However, if the two complementary lines are run adjacent and parallel to each other on the chip, this is a very unlikely situation.
The UV flip-flop of the present invention has many potential embodiments. However, from a conceptual standpoint it can be considered an SR flip flop preceded by a front end circuit that converts the illegal 1-1 input state to a memory state (i.e., the output will remain at its previous state responsive to a 1-1 condition at its two input terminals). For a NOR-gate realized SR flip-flop, the front-end circuit may comprise two AND-gates, the first one having its first input coupled to the first of the complementary signal paths and its second input coupled to the inverse of the second of the complementary signal paths. The second AND-gate has a first input coupled to the inverse of the first of the complementary signal paths and a second input coupled to the second of the complementary signal paths. The outputs of the first and second AND-gates are coupled, respectively, to the S and R inputs of a normal SR flip-flop.
This front end circuit has no affect with respect to input conditions 0-0, 1-0 and 0-1 on the complementary input lines. However, it converts a 1-1 input signal to a 0-0 output signal, thus causing the 1-1 input state to the UV flip-flop to also be a memory state.
REFERENCES:
patent: 4525635 (1985-06-01), Gillberg
patent: 5729449 (1998-03-01), Takaka et al.
patent: 5739706 (1998-04-01), Okamoto
patent: 5889429 (1999-03-01), Kobayashi et al.
patent: 5955901 (1999-09-01), Kikuchi et al.
patent: 3-91314 (1991-04-01), None
patent: 403258015 (1991-11-01), None
Agere Systems Guardian Corp.
Lam Tuan T.
Synnestvedt & Lechner LLP
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