Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-09-27
2002-03-12
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S758000
Reexamination Certificate
active
06355969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the programming of devices of semiconductor chips, and more particularly, to the forming of programmable devices and the selective programming of such devices by way of electromigration induced currents.
2. Description of the Related Art
Recently, there have been many advances in the fabrication of semiconductor devices, which have led to the continued development of smaller and smaller semiconductor chips. Due to these advances, miniature chips are finding a number of new applications. Such applications include, for example, automated teller machine (ATM) cards, identification cards, security access cards, set-top boxes, cellular phones, and the like. The integrated chips bring these type of applications substantially more intelligence than was previously possible with magnetic strips and other static data storage. Applications such as these, however, require chips that can be programmed with specific passwords, programs, or codes in order to store information that is either unique to the user, or specific to the chip.
Traditionally, the manufacturer of the chip may be required to program codes or set wiring after the chip is packaged using laser fuse technology or before packaging using antifuse technology. As is well known to those skilled in the art, laser fuse technology requires that a fuse structure (that is in the form of a metal line) be blown apart to prevent future electrical conduction. Although fuse technology is capable of providing programmability, a polysilicon-type fuse (which is most common), necessarily prevents a certain amount of chip area from being used for active circuitry. Typically, fuses that utilize a laser for obliteration need to be placed sufficiently away from active circuitry because of the potential for collateral damage to other circuit elements from the laser pulse or by subsequent damage associated with damage to the passivation and intermetal oxides (IMO) layers at the fuse locations. Additionally, fuses that require laser obliteration need to adhere to specific spacing requirements to ensure that there is no thermal coupling between devices or inadvertent programming of other fuses.
Antifuse technology, on the other hand, defines a link between two metal layers by forming links through an amorphous silicon layer. As can be appreciated, implementing antifuse structures into a custom chip design requires a number of special fabrication operations to make the antifuse structures. In addition, some antifuse structures require even more chip area than fuses. More importantly, the programming of antifuses requires that enough current is passed between two metal layers that a silicided link is created between the selected metal lines. Although antifuse technology can be used, it is also known to be somewhat unreliable. That is, fuses that appear programmed at one point in the chip's operational life may become de-programmed unexpectedly. Most importantly, the fabrication of limited number of antifuse devices onto an application specific integrated circuit (ASIC) may drive the cost of fabrication too high to make the chip practical for certain consumer applications.
In view of the foregoing, there is a need for a method of making a programmable structure, which can be cost effectively fabricated and is capable compactly being designed into any type of integrated circuit structure. There is also a need for programmable structures that do not occupy chip area that needs to be used for active devices and do not cause damage to neighboring devices when programmed.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a programmable structure that can be internally programmed to form a hard-wired link, and methods for making the programmable structure. The internal programming is preferably completed by externally providing programming signals to pads of a semiconductor chip having the programmable structures. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a programmable structure is disclosed. The programmable structure includes a first lower metallization line that is defined on a first metallization layer. A second lower metallization line is defined on the first metallization layer, and the first and second lower metallization lines are electrically connected. Further included is a first and second upper metallization lines defined on a second metallization layer. A conductively filled via electrically connects the second lower metallization line to the second upper metallization line, and an eroded via is defined between the first lower metallization line and the first upper metallization line. The programmable structure further includes an electrical connection that is defined between a first point on the second upper metallization line and a second point on the first lower metallization line. The electrical connection is capable of forming an electron flow originating at the second point of the first lower metallization line and leading to the first point of the second upper metallization line, such that electron flow causes metallization of the first lower metallization line to flow into the eroded via and form a hard-wired link.
In another embodiment, a method for making a programmable structure in a semiconductor chip is disclosed. The method includes forming a first metallization layer such that it includes a first lower metallization line and a second lower metallization line. The first and second lower metallization lines are configured to be electrically connected or defined as a single line (e.g.,
204
′ of FIG.
3
A). Then, a second metallization layer is formed, such that the second metallization layer includes a first upper metallization line and a second upper metallization line. A conductively filled via to electrically connect the second lower metallization line to the second upper metallization line is formed, and an eroded via between the first lower metallization line and the first upper metallization line is formed. The method then includes applying a current between a first point on the second upper metallization line and a second point on the first lower metallization line. The applied current is configured to generate an electron flow originating at the second point of the first lower metallization line and leading to first point of the second upper metallization line, such that electron flow causes metallization of the first lower metallization line to flow into the eroded via to define a hard-wired link. Preferably, the current is applied by way of the chip' s bonding pads, either directly or through an on-chip programming circuit. The eroded via is preferably formed by submersing the programmable structure into a basic solution after a plasma etching operation. The submersing is configured to cause a tungsten material in a tungsten plug to become the eroded via.
In yet another embodiment, a method for making a programmable structure in a semiconductor chip is disclosed. The method includes: (a) forming a lower metallization layer; (b) forming an upper metallization layer, the upper metallization layer having a first portion and a second portion; (c) forming an eroded via between the lower metallization layer and the first portion of the upper metallization layer; (d) forming a conductive via between the lower metallization layer and the second portion of the upper metallization layer; and (e) applying a current between the lower metallization layer and the second portion of the upper metallization layer. The current being configured to cause electromigration in the lower metallization layer such that some of the electromigration fills the eroded via between the lower metallization layer and first portion of the upper metallization layer.
It should be appreciated that the pr
Bothra Subhas
Skala Stephen L.
Estrada Michelle
Fourson George
Martine & Penilla LLP
Philips Electronics North America Corporation
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