FIR decimation filter and method

Details FIR decimation filter and method FIR decimation filter and method

2000-12-14

2002-07-30

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S319000

Reexamination Certificate

active

06427158

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to use of FIR filters as decimation filters, and more particularly to a FIR decimation filter which allows a reduction in the amount of integrated circuit chip area required, and which also reduces power dissipation, especially for high-performance applications.
Prior art
FIG. 1
shows a conventional finite impulse response filter
2
. (Finite impulse response filters are hereinafter referred to as FIR filters.) FIR filter
2
includes a suitable number of delay elements
4
,
6
,
8
. . .
14
connected sequentially, so that the input signal IN is applied to the input of delay element
4
, the output of which is connected to the input of delay element
6
. The output of delay element
6
is connected to the input of the next delay element
8
, and so forth. Each of the delay elements “corresponds” to another of the delay elements so as to accomplish a desired filtering operation. For example, the first delay element
4
corresponds to the last delay element
14
, and the second delay element
6
corresponds to the next-to-last delay element
12
, and so forth. One commonly used type of FIR filter is a linear phase filter. The coefficients of a linear phase filter have symmetric features, and because of the symmetric features, the corresponding data bits referred to can be advantageously paired prior to reduce the number of multiplications required.
Specifically, outputs of the corresponding delay elements are added together, and the resulting sum is multiplied by a coefficient. For example, the outputs of corresponding delay elements
4
and
14
are added together by adder
16
, and the result is multiplied by a first coefficient a
1
by means of a first multiplier
17
. Similarly, the outputs of corresponding delay elements
6
and
12
are added by adder
18
, and the resulting sum is multiplied by a coefficient a
2
by means of a multiplier
19
, and so forth. The results of the adding operations and coefficient multiplication operations then are all summed by an adder
22
to produce an output signal OUT. The delay elements typically are implemented by using D-type flip-flops, which when connected as described above, constitute a shift register in which the flip-flop outputs constitute tap points. At least one adder, such as adder
16
, and at least one multiplier, such as multiplier a
1
, are required for each corresponding pair of flip-flops, if the adder and multiplier are operating at the same speed as the rate at which the incoming data is being clocked into the shift register.
However, the fact that the output rate of a decimation filter is much lower than its input rate usually allows some hardware, especially adders and multipliers, to be shared in a simplified design. If the multipliers and associated accumulators are allowed to operate at multiples of the rate at which the incoming data is being clocked into the shift register, then multiple pairs of flip-flops of the shift register can share the same multiplier and accumulator circuitry.
Nevertheless, each D-type flip-flop in prior art
FIG. 1
still needs to be individually accessed with corresponding control circuitry to accomplish the required pre-adding, and also needs to transfer its content to the next successive D-type flip-flop. The excessive wiring, complex routing, and corresponding control logic circuitry of the FIR filter shown in
FIG. 1
result in excessive use of surface area on an integrated circuit chip.
Prior art
FIG. 2
shows another 16 tap FIR filter
30
, which is implemented as a “dual-loop shift register” that may be used in some analog-to-digital converters. As shown in part (a) of
FIG. 2
, the dual loop shift register
30
includes a first shift register chain
38
in which data bits Z
1
,
2
. . .
8
are stored, and a second shift register chain
36
in which data bits Z
9
,
10
. . .
16
are stored. The output of flip-flop Z
8
is provided as an output at end
34
of shift register chain
38
and also is connected to the input of flip-flop Z
16
. Bit Z
9
provided as an output at end
34
of shift register chain
36
.
The configuration illustrated in parts (a)-(d) of
FIG. 2
is for a 16-bit oversampling analog-to-digital converter (ADC). With FIR filter
30
implemented as a dual-loop shift register, data signals Zi, wherein the index I is equal to
0
,
1
,
2
. . . , are accessed only at the ends
32
and
34
of shift register chains
36
and
38
. Larger values of the index letter I correspond to the most recent values of the bits Zi of the incoming input data signal. The flow of data through FIR filter
30
is illustrated in the sequence shown in
FIG. 2
, the initial state of FIR filter
30
being shown in part (a) of FIG.
2
. After one data shift or clock cycle, the data bits are located as shown in part (b) of FIG.
2
. After the next seven data shifting operations, the 16-bit shift register is operationally configured as shown in part (c) of FIG.
2
. After one more clock cycle, the output of the shift register chain
38
is connected to the input of shift register chain
36
again, as shown in part (d) of
FIG. 2
, to start a new cycle. This operation aligns the shifted data so that corresponding bits of data can be added in a fashion analogous to that for the FIR filter of prior art FIG.
1
.
Although the shift register configuration of
FIG. 2
may require less surface area of an integrated circuit chip because it does not require routing of the output of each flip-flop of each shift register chain to the various adders as in the prior art FIR filter of
FIG. 1
, the FIR filter of
FIG. 2
requires calculating mathematical functions by clocking the two shift register chains with a significantly higher speed than the data input rate. In this 16 tap filter, the shift register chain has to be operated at least about eight times faster than the incoming data rate. This high-speed clocking substantially increases power dissipation. Also, in some cases the clocking speed required for calculating the mathematical functions may be too high to be practical using available technology.
U.S. Pat. No. 5,170,368 discloses a digital decimation filter in which shift registers are used to take incoming data. A bank of switches is deployed between the shift registers and the accumulator output to provide, in conjunction with appropriate control circuitry, selective access to the content of the various shift register flip-flops to accomplish the data processing. U.S. Pat. No. 5,838,725 discloses a floating point digital transversal filter in which shift registers are used to take incoming data. The filter output result is generated through a ROM lookup table. U.S. Pat. No. 4,817,025 discloses a digital filter in which shift registers are used to take incoming data. Every register output is used for calculation every clock cycle. The digital filter is used in an interpolation filter. U.S. Pat. No. 5,193,070 discloses a transversal filter circuit having circuits that include bidirectional shift registers for serial multiplication. It is used to shift coefficients up or down for serial multiplication. U.S. Pat. No. 5,297,069 discloses a finite impulse response filter (FIR filter) in which shift registers are replaced by recirculating addressable memory. The shifting structure has feedback, making it a recirculating structure.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide an FIR decimation filter which consumes less power and requires less integrated circuit chip area than the above described prior art.
It is another object of the invention to provide a generic design methodology for an FIR decimation filter.
Briefly described, and in accordance with one embodiment thereof, the invention provides an FIR decimation filter including a shift register (
51
) including M flip-flops arranged in M/R rows (
52
,
54
,
56
,
58
) of R bits each, wherein M/R is an integer and R is the decimation ratio of the FIR decimation filter. The shift register has an input for receiving serial digital input information. Hal

Affiliated with

Also associated with

Rating

FIR decimation filter and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FIR decimation filter and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIR decimation filter and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2883740