Interlock control of asynchronous data transmission between a ho

Details Interlock control of asynchronous data transmission between a ho Interlock control of asynchronous data transmission between a ho

1978-05-15

1981-01-06

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 100

Patent

active

042440181

ABSTRACT:
An interlock circuit is set forth which provides for controlling asynchronous data transfers between a host processor and a plurality of microprocessors via a common buffer. The interlock circuit consists of an interconnection of latches arranged so that the first processor initiating a transfer request inhibits all remaining processors from activating their respective transfer requests. Each processor upon terminating a data transfer clears its associated transfer request. The host processor can clear all transfer requests upon command.

REFERENCES:
patent: 3214739 (1965-10-01), Goutanis et al.
patent: 3566357 (1971-02-01), Ling
patent: 3603935 (1971-09-01), Moore
patent: 3820084 (1974-06-01), Jones
patent: 3934232 (1976-01-01), Curley et al.
patent: 3976979 (1976-08-01), Parkinson et al.
patent: 3988716 (1976-10-01), Fletcher et al.

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