Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-06-26
2002-08-27
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S038000, C216S079000, C438S723000, C438S740000, C438S743000
Reexamination Certificate
active
06440869
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming a capacitor in DRAM, particularly relates to a method of forming the hemispherical silicon grain (HSG) with strong mechanical strength.
BACKGROUND OF THE INVENTION
As the semiconductor memory device becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks and it will cause the capacitance reduce of the capacitor. Owing to the leakage current, however, it is necessary to refresh the capacitor continuously in order to keep the stored state, especially when the capacitance of the capacitor is limited. Furthermore, the area reduction of the capacitor occupied will cause the capacitor to be disturbed by the alpha particle more easily.
Until now, there has been much effort directed to keep a relatively large capacitance of the capacitors in order to achieve a high signal to noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference) as the memory device becomes highly integrated. As the followings, there are some approaches to increase the storage capability of the capacitor while the area occupied by the capacitor maintains small enough. (1) substituting a high capacitance material for traditional material to increase the storage charges per unit area of the capacitor, for example: the substitution the of Ta
2
O
5
and TiO
2
for SiO
2
. (2) decreasing the dielectric layer thickness of the capacitor: because of the Fowler-Nordheimn tunneling effect, the dielectric layer thickness is limited to a minimum value and one can not improve the capacitor too much by this method. (3) variation the shape of the capacitor electrodes: the capacitor may have protrusions, cavities, etc., to increase the surface area of the capacitor electrode. (4) increasing the contact area between the conductive layer acting as the electrode of the capacitor and the dielectric layer: the surface between the dielectric layer and the conductive layer can be varied to a ragged type surface and not be even a plain surface anymore.
The aforementioned third approach, it has been widely used and a crown-shaped or an U-shaped capacitor has been developed. For the last one method, one type of the surface variation is a ragged polysilicon layer or hemispherical grain (HSG) polysilicon. The combination implementing of these two methods is as following description.
FIG. 1
is a cross section view illustrating the step where capacitor fabrication begins. There are two word lines structure
102
, active areas
110
and field oxide region
103
. The active area
110
is isolated from other active area in a DRAM array by a field oxide region
103
, and one of the word line structure
102
is positioned over field oxide region
103
.
As shown in
FIG. 1
, the word line structure
102
comprise a first silicon oxide layer
106
, a polysilicon layer
108
formed on the first silicon layer
106
, a refractory layer
105
formed on the polysilicon layer
108
, a horizontal spacer layer
104
formed one the refactory layer
105
and a pair of sidewall spacer
112
formed vertically along the side wall of the word line structure
102
. The spacer
112
and
104
is silicon nitride or silicon dioxide material, and are used to protect the word line structure
102
from any etching process or act as a shield to prevent dopants atoms entering the channel region. Furthermore, during the operation of the DRAM, the spacer
112
and
104
provide electrical isolation between the gate electrode
102
and the active area
11
O.
FIG. 2
which is a cross sectional view of a semiconductor substrate illustrates the steps of forming a etch stop layer
116
, sacrificial layer
118
, masking layer
120
and a photoresist layer
122
in the prior art. An conformal etch stop layer
116
, comprising silicon dioxide layer preferably, is formed on the substrate
100
in FIG.
1
. Then, a sacrificial layer
118
with preferred polysilicon material is deposited conformally on the etch stop layer
116
. The preferred polysilicon sacrificial layer
118
may reduce the stress during process. Following the sacrificial layer
118
deposition, a masking layer
120
preferably comprising borophosphosilicate glass (BPSG) is deposited and planarized to a selected thickess sufficient to fill all the gaps between the adjacent word line structure
102
and to coat the word line structure
102
so as to provide a planar upper surface
121
. Afterward, a photoresist layer
122
is deposited on the masking layer
120
.
Referring to
FIG. 3
, which is a cross sectional view of a semiconductor substrate, illustrates the step of forming a contact hole
126
in the prior art. The photoresist layer
122
is patterned using photolithography process to create a contact hole
126
in the photoresist layer
122
. Next, the masking layer
120
and the sacrificial layer
118
are etched in sequence by using the patterned photolithograpy layer
122
, and the contact hole
126
is created in the masking layer
120
and the sacrificial layer
118
.
FIG. 4
which is a cross sectional view of a semiconductor substrate illustrates the steps of removing the etch stop layer
116
and forming a HSG polysilicon layer
128
. The etch stop layer
116
is processed by dry etching process to expose the active area
110
and part of the word line structure
102
. Then, the remaining photoresist layer
122
is removed by dry etching process and a hemispherical grain (HSG) polysilicon layer
128
is then formed on the surface of the contact hole
126
and on the upper surface of the masking layer
120
. The HSG polysilicon layer
128
forms the storage plate or the bottom electrode of the future capacitor.
Referring to
FIG. 5
, after the formation of the HSG polysilicon layer
128
, the substrate
100
is process with CMP (chemical mechanical planarization). The HSG polysilicon layer
128
on the upper surface of the masking layer
120
is removed.
Referring to
FIG. 6
, following the CMP step, the remaining masking layer
120
and the remaining sacrificial layer
118
are removed in sequence by selective etching process. The wall portion
127
of the HSG polysilicon layer
128
significantly increases the surface area of the contact area. However, the connection of every hemispherical grain on the wall portion
127
is located on the connection of the grain edge and is very weak, the wall portion
127
is insufficient with the mechanical strength. The insufficient mechanical strength may induce the crack of the wall portion
127
, and lose the capability of the capacitor formed by changing the shape of the capacitor and increasing the contact area.
Therefore, it is really required to improve the mechanical strength.
SUMMARY OF THE INVENTION
The present invention provides a manufacturing process for increasing the mechanical strength of the HSG layer.
In the present invention, two word line structures, active areas are provided on the substrate. First, a conformal etch stop layer is deposited on the active region and said word line. A sacrificial layer and a mask layer is formed on the etch stop layer. Then, the substrate is process with CMP to planarize the top surface of the mask layer. Then, a contact hole is formed in the sacrificial layer, mask layer and the etch stop layer to expose portions of the active region and the word lines structures.
A polysilicon layer with the thickness about 50 to 2000 angstroms is formed on the surface of the contact hole and the top surface of the masking layer. Next, a hemishperical grain (HSG) layer with the thickness about 10 to 500 angstroms is formed on the polysilicon layer. Then, the substrate is process with CMP to remove the portions of the polycilicon layer and the HSG layer on the top surface of the masking layer. And the masking layer and the sacrificial layer are removed by etching process. Finally, a dielectric layer is deposited on the HSG layer and a conductive layer is deposited on the dielectric layer to form the capacitor.
REFERENCES:
patent: 6187623 (2001-02-01),
Bacon & Thomas
Powell William A.
Vanguard International Semiconductor Corporation
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