Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-08-27
2002-09-17
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S693000, C438S745000
Reexamination Certificate
active
06451696
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
The entire disclosure of Japanese Patent Application No. 10-243868, filed on Aug. 28, 1998, priority of which is claimed under 35 USC 119, including specification, claims, drawings, and summary are incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
The present invention relates to methods for reclaiming wafer substrates, more particularly to a method for reclaiming a used semiconductor wafer substrate so that the substrate is of a quality which is substantially comparable to a prime grade wafer used in the production of semiconductor devices.
BACKGROUND
In the production of semiconductor devices, two grades of single crystal silicon wafers, e.g., a prime grade and a test grade, are used. The prime grade wafers are used for producing actual semiconductor devices, and the test grade wafers are used to determine whether or not the production process is sufficiently satisfactory. The quality standard for the prime grade is more stringent than that for the test grade. Semiconductor manufacturers use test grade wafers having the quality comparable to that of prime grade wafers by preference. Such test grade wafers are expensive compared to general test grade wafers. A typical used semiconductor wafer has a doped and/or diffused zone beneath the original front surface, and conductive and dielectric layers, which are formed on the doped or diffused zone.
In reclamation of a wafer substrate, both the surface layers and the doped or diffused zone beneath the wafer surface are removed. Used wafers delivered to reclamation plants are made of various materials and have a variety of surface structures and subjacent layers. For example, some wafers used for measurement of film thickness have several surface layers, and some wafers rejected in the production process have their own film structures, combinations of film materials, and doped elements.
A variety of conventional methods for reclaiming used semiconductor wafers are in use. Since these methods remove large amount of material from the surface as compared to the thickness of surface layers and diffused or doped zones, a wafer can be recycled only once or twice.
The most frequently used conventional method is a chemical etching process. For example, U.S. Pat. No. 3,923,567 discloses a process for dipping a wafer substrate having a surface layer into an etching bath containing sulfuric acid to remove organic substances, hydrochloric acid and nitric acid to remove metallic substances, and hydrofluoric acid to remove oxides and nitrides. According to this patent, a preferable etching rate is 12 &mgr;m/sec. A mixture of nitric acid (HNO
3
) and hydrofluoric acid (HF) is frequently used as an etching solution for reclamation, since the mixture can remove most films and doped or diffused zones.
Wafers can also be reclaimed by a lapping process. The lapping process can remove various materials on the wafer regardless of the surface structure and pattern and the constituents on the wafer, unlike the chemical etching process. In the lapping process, a wafer is pressed against a rotating metal plate, while a lapping solution is supplied between the wafer surface and the plate (the lap). In double-side lapping, a wafer is pressed between a pair of metal plates (generally, cast-iron plates), which rotate in the opposite directions. The abrasive grains collide with the wafer surface to generate small cracks beneath the wafer surface and to remove the surface materials.
U.S. Pat. No. 5,855,735 discloses a method for decreasing sub-surface damage by a lapping process. This method comprises removing surface material by inducing micro-fractures in the surface using a rotating pad and an abrasive slurry, and chemically etching the surfaces of the wafer until all micro-fractures are removed therefrom.
Another method for reclaiming the wafer is a polishing process. In single-side polishing, a wafer surface is pressed onto a rotating pad, while a polishing solution containing abrasive grains is supplied between the pad and the wafer surface to remove the surface materials. In double-side polishing, a wafer is sandwiched between a pair of pads which rotate in opposite directions, while fine abrasive grains are supplied therebetween to remove small amount of material from surface. Thus, this method can significantly reduce subsurface damage compared to the above-mentioned lapping process.
The most frequently used polishing process is chemical-mechanical polishing using a polishing solution containing various chemicals. That is, the chemicals contribute to cleaving or weakening inter atomic bonds at the surface of a workpiece to be polished, while abrasive grains enhance wiping effects of the surface of the workpiece. Silicon wafers are usually subjected to single-side polishing using a polishing solution containing fine alkaline colloidal silica particles having diameters of 1 &mgr;m or less, in addition to potassium hydroxide, ammonium hydroxide and an organic amine. According to the Journal of The Society of Grinding Engineers, Vol. 40, No. 1, p. 19 (1996), a variety of abrasive grains, such as alumina, titania, zirconia, ceria, and silica, have been tested for polishing silicon wafers, and all of the abrasive grains other than silica cause oxidation induced stacking fault (OSF). Various opinions are proposed for the fact that alkaline colloidal silica is specifically suitable for polishing of silicon wafers. Although chemical-mechanical polishing, as a combination of mechanical polishing by fine silica particles and chemical etching by alkaline components, yields such specific polishing characteristics, details are still unknown. Polishing is performed to remove surface damage formed in the lapping step and to produce a mirror surface.
Chemical-mechanical polishing can also remove various films on the wafer surface. In recent production processes of semiconductor devices, multilayered configurations have been common. Since the multilayered configuration causes a difference in level of the film surface, the configuration will result in defocusing during the exposure step of the pattern of the device. Thus, the film surface of the multilayered configuration is generally planarized. Chemical-mechanical polishing is employed for planarization of the film surface to effectively remove particular film components so that the flatness of the film surface may be improved. Accordingly, chemical-mechanical polishing requires high selectivity for removal of the film components so that a specified component is more effectively removed than other components.
For example, the planarization of the aluminum wiring layer uses an acidic polishing solution containing aluminum oxide abrasive particles, hydrogen peroxide, and iron nitrate so that silicon oxide as a component of an dielectric layer is removed as little as possible. In contrast, the planarization of the dielectric layer composed of silicon oxide or the like uses an alkaline polishing solution containing silicon oxide (fumed silica) abrasive grains, potassium hydroxide (KOH), ammonium hydroxide (NH
4
OH), and an organic amine so that the metallic wiring layer is removed as little as possible.
Such a chemical etching process can simply and uniformly reclaim the etching surface when the reclaimed wafer has a relatively small size, since the wafer has a relatively simplified film configuration. This chemical etching process, however, is not effective for uniform reclamation of a large wafer having a complicated surface film configuration and containing many components. Although many types of etching solutions must be prepared for effectively etching individual layers formed on a wafer, these etching solutions are not always useful for etching other wafers having different film components and configurations.
When each layer has a pattern, the etching rate of a portion of a specified layer is different from the etching rate of another portion of the layer. Thus, the bottom most layer inevitably has an irregular surface. For example, tungsten silicide (WSi)
Hara Yoshihiro
Inoue Hidetoshi
Suzuki Tetsuo
Takada Satoru
Kabushiki Kaisha Kobe Seiko Sho
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Binh X
Utech Benjamin L.
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