Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2000-09-07
2002-09-10
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C438S613000, C438S615000
Reexamination Certificate
active
06448646
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device-mounting construction having solder bumps serving as external terminals, and more particularly to a semiconductor device-mounting construction capable of achieving an excellent connection reliability of solder bumps. This invention also relates to a method of inspecting such a semiconductor device-mounting construction.
BACKGROUND OF THE INVENTION
With the highly-integrated design of semiconductor devices, there have now been developed semiconductor devices having an increased number of external terminals (pins). There have been used two methods of achieving such a semiconductor, and one is a method in which in a conventional quad flat package (hereinafter referred to as “QFP”) having leads serving as external terminals, the pitch of the terminals is made finer and smaller, thereby increasing the number of pins. According to this method, there has been developed a QFP of the type in which the terminal pitch is reduced to 0.3 mm. However, the terminals are arranged in a one-dimensional manner, and therefore it is said that the upper limit is 400 pins in view of the dimensions of the semiconductor device which can be mounted.
The other method is one in which solder bumps are arranged in a two-dimensional manner on a reverse surface of a semiconductor device, and are used as external terminals. A semiconductor device of this construction is commonly called a ball grid array (hereinafter referred to as “BGA”). The detailed construction of a BGA is disclosed, for example, U.S. Pat. No. 5,216,278 and NIKKEI ELECTRONICS No. 601, page 59.
Recently, there have been developed a BGA-type semiconductor device whose size is reduced to the size of a semiconductor chip. This is called a chip-size package (hereinafter referred to as “CSP”). The detailed construction of a CSP is disclosed in NIKKEI ELECTRONICS No. 668, page 139. Further, Japanese Patent Laid-Open Publication No. 6-504408 (W092/05582) discloses a CSP of the type in which a tape, having external terminals, is provided on a circuit-forming surface of a semiconductor chip through a soft or elastic material (elastomer resin), and the external terminals are electrically connected to electrodes of the semiconductor chip. Japanese Patent Unexamined Publication No. 6-224259 discloses a construction in which a semiconductor chip is mounted on a ceramic substrate having through holes, and electrodes are formed on the opposite surface of the ceramic substrate, and the semiconductor device is mounted on a printed circuit board. Japanese Patent Unexamined Publication No. 6-302604 discloses a CSP of the type in which a metallic wiring pattern is formed on a circuit-forming surface of a semiconductor chip, and external terminals are provided on this wiring pattern.
What becomes a large problem with the BGA-type semiconductor device, using the solder bumps as the external terminals, is the connection reliability of the solder bumps. If the coefficient of linear expansion of the semiconductor device is different from that of a mounting board, a strain develops in the solder joint portions in accordance with a temperature change, and when this is repeated, a thermal fatigue failure may occur. In the conventional semiconductor device, such as a QFP, having leads serving as external terminals, the leads absorb this thermal deformation, thereby reducing a strain developing in the solder, so that the thermal fatigue failure can be prevented. However, in the BGA-type semiconductor device, thermal deformation is applied directly to the solder bumps.
Therefore, in the type of BGA-type semiconductor device (as disclosed in U.S. Pat. No. 5,216,278) using a printed circuit board, there is employed a method in which the printed circuit board of the semiconductor device and a mounting printed circuit board are made equal in the coefficient of linear expansion to each other, thereby preventing thermal deformation. However, even if the two printed circuit boards are made of the same kind of material, the two boards are different in the coefficient of linear expansion from each other usually by an amount of about 2×10
−6
/° C. because of variations in the coefficient of linear expansion of the material.
Among the above-mentioned prior art devices, it is thought that the semiconductor device, disclosed in Japanese Patent Laid-Open Publication No. 6-504408, is the type in which the solder fatigue failure is most taken into consideration, and the reliability is the highest. In this semiconductor device, the tape, having the external terminals, is provided on the semiconductor chip through the elastomer resin, and the external terminals are electrically connected to the electrodes of the semiconductor chip, and the solder bumps are joined to the external terminals. Therefore, the thermal deformation due to the difference in the coefficient of linear expansion between the semiconductor chip and the mounting board can be absorbed by the elastomer, thereby preventing the thermal fatigue failure of the solder bumps. However, the size of this semiconductor device coincides with the size of the semiconductor chip, and therefore the number of pins is limited.
And besides, voids, which are due to insufficient wetting and the involvement of gas during joining of the solder, are present in the solder joint portion. From the study by the inventors of the present invention, it is clear that these voids are a factor reducing a fatigue life of the solder joint portion, and its contents are described in “Current Japanese Material Research, No. 2(1987), pp.235” published by the Society of Materials Science, Japan. With respect to this problem, the target of the process design is to reduce the ratio of the total area of voids to the total cross-sectional area of the joint portion (commonly referred to as “void ratio”). Namely, efforts have been made to reduce the total area of the voids.
As described above, the conventional BGA-type semiconductor devices still have the problem with respect to the connection reliability of the solder bumps regardless of their construction. Particularly, no consideration has been given to a reduced thermal fatigue life due to the influence of the voids existing in the solder bump joint portion.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a BGA-type semiconductor device which overcomes the drawbacks of the above conventional BGA-type semiconductor devices, and achieves an excellent connection reliability of solder bumps.
The above object has been achieved by limiting voids, present in a solder joint portion of a BGA-type semiconductor device, to a predetermined size.
A semiconductor device-mounting construction of the present invention comprises a semiconductor device having a plurality of electrodes formed on one main surface thereof, a printed circuit board having a wiring pattern formed on one main surface thereof, and a plurality of solder bumps interposed between the plurality of electrodes and the wiring pattern to electrically connect the semiconductor device and the printed circuit board together, and this semiconductor device-mounting construction has the following features:
(1) All of voids, which are present in an interface of each of those of the plurality of solder bumps (which are disposed closest to an outer peripheral edge of the semiconductor device), joined to the semiconductor device, are fine, and generally uniform in size.
A shearing strain, developing in the solder bump, becomes larger as the distance between the solder bump and the center of the semiconductor device becomes larger, and therefore those solder bumps, disposed closest to an outer periphery edge of the semiconductor device, are subjected to a severest condition. Therefore, if all of the voids, which are present in the interface of the solder bump under this severest condition, are fine, and generally uniform in size (that is, uniform voids), the concentration of the strain will not occur, so that the reliability of the solder bump joint portion is enhanced
Honda Michiharu
Kitano Makoto
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Vigushin John B.
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