Semiconductor memory and method of controlling the same

Details Semiconductor memory and method of controlling the same Semiconductor memory and method of controlling the same

2000-11-08

2002-08-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230060

Reexamination Certificate

active

06434080

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H 11-316487 filed on Nov. 8, 1999, in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory, such as, EEPROM, having a built-in boosted voltage generator and a method of controlling such a semiconductor device.
Recent EEPROM-flash memories are provided with an automatic data-writing function. In this function, input of a write command, an address and data initiates automatic data writing and automatic verification of the written data in the chip. Moreover, the input of an erase command and an address initiates automatic erasing and automatic verification of data erasing and the erased data in the chip.
Well known NOR-type flash memories have a small number of sense-amplifiers compared to the bit lines in a memory cell array. T he number of the sense-amplifiers, for example, corresponds to just one word (16 bit)-data. Data writing to a plurality of addresses (words) thus requires designation of the next write address and data for re-input of a write command whenever a writing operation for the former address is completed.
EEPROM-flash memories therefore require a very long data-writing period to rewrite a large amount of data for program or audio data recording.
A boosted voltage generator installed in the EEPROM-flash memory is turned on and off for a writing operation to each address in an automatic writing operation, thus requiring a waiting period at an initial writing stage to each address for stable voltage generation. Such a waiting period also makes for a long writing period and increases power consumption.
Another type of NOR-type flash memory for automatic data writing with one page-internal data (a plurality of words corresponding to one page) requires a data latch for holding one page-data in addition to sense-amplifiers for one word, thus resulting in a complex structure and control.
SUMMARY OF THE INVENTION
A purpose of the present invention is to provide a semiconductor memory and a method of controlling the memory a smaller data-writing period and less power consumption.
The present invention provides a semiconductor memory including: a memory cell array; a boosted voltage generator for generating a boosted voltage; a decoder for selecting memory cells in the memory cell array in response to an address signal; and a controller for activating the voltage generator in response to input of a first command, and keeping the voltage generator in active during repeated input of a second command for controlling the voltage generator, following to the first command.
Moreover, the present invention provides a semiconductor memory including: a memory cell array; a boosted voltage generator for generating a boosted voltage; a decoder for selecting memory cells in the memory cell array in response to an address signal; and a controller, having an input terminal, for controlling the voltage generator to be in an active or inactive state. The semiconductor memory has a regular operation mode in which the voltage generator is controlled to be the active or the inactive state by means of a first control signal output by the controller in response to a predetermined signal supplied to the input terminal, and a successive operation mode in which the voltage generator is kept active by means of a second control signal output by the controller in response to another predetermined signal supplied to the input terminal.
Furthermore, the present invention provides a semiconductor memory including: a memory cell array; a boosted voltage generator for generating a boosted voltage; a decoder for selecting memory cells in the memory cell array in response to an address signal; and a controller for activating the voltage generator for a predetermined period in response to input of a first command, and keeping the voltage generator active in response to input of a second command within the period, while deactivating the voltage generator when no input of the second command is received within the period.
Moreover, the present invention provides a semiconductor memory including: a memory cell array; a boosted voltage generator having a first booster circuit that is controlled to be in an active or inactive state to generate a boosted voltage, and a second booster circuit that is always controlled in an active state to generate another boosted voltage; a regulator for regulating the output level of the voltage generator according to an operation mode; a decoder for selecting memory cells in the memory cell array in response to an address signal; and a controller for continuously activating the first circuit for a period during repeated input of a plurality of address signals and data to be written in response to input of a predetermined command.
Furthermore, the present invention provides a semiconductor memory including: a memory cell array having nonvolatile memory cells; a boosted voltage generator for generating a boosted voltages for data-writing and data-reading to and from the memory cell array; a sense-amplifier for sensing data read from the memory cell array; a decoder for selecting memory cells in the memory cell array in response to an address signal; and a controller for controlling an automatic writing operation to write data and verify written data to said memory cell array based on input of a write command, an address and data, and to verify written data. The semiconductor memory has a successive writing mode in which a booster circuit of the voltage generator for data-writing is kept in an active state without returning to an inactive state for completion of writing to each address when writing to a repeatedly-entered plurality of addresses.
Moreover, the present invention provides a semiconductor memory including: a memory cell array; a boosted voltage generator for generating a boosted voltage; a decoder for selecting memory cells in the memory cell array in response to an address signal; and a controller for providing a command to control the voltage generator. The command has a mode wherein the voltage generator is turned on and continues operation until input of the command to the controller to turn off the voltage generator.
Moreover, the present invention includes a semiconductor memory including: a memory cell array having nonvolatile memory cells; a boosted voltage generator for generating a boosted voltage for data-writing and data-reading to and from the memory cell array; a sense-amplifier for sensing data read from the memory cell array; a decoder for selecting memory cells in the memory cell array in response to an address signal; and a controller for controlling an automatic writing operation to write data and verify written data to the memory cell array based on the input of a write command, an address and data, and to verify written data. An internal timer level for automatic operation varies from a level for regular operation while a command is input to the controller, the command has a mode in which the voltage generator is turned on and continues operation until the input of the command to the controller to turn off the voltage generator.
Moreover, the present invention provides a method of controlling a semiconductor memory having a built-in boosted voltage generator for generating a boosted voltage for a write-operation control, comprising the steps of: setting a successive writing mode in which the voltage generator is kept active by input of a first command, an address signal and data to be written; and writing data to a plurality of addresses while the voltage generator is kept active by repeated input of a second command and an address signal and the corresponding data to be written, following the first command.


REFERENCES:
patent: 6031411 (2000-02-01), Tsay et al.
patent: 6118699 (2000-09-01), Tatsumi et al.
patent: 11016368 (1999-01-01), None

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