Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-11-16
2002-07-09
Gandhi, Jayprakash N. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S703000, C361S715000, C361S744000, C361S804000, C257S685000, C257S686000, C257S723000, C257S724000
Reexamination Certificate
active
06418033
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to microelectronic packages and packaging methods.
BACKGROUND OF THE INVENTION
In packaging microelectronic devices such as integrated circuits (also referred to as integrated circuit chips or simply as chips) on printed circuit boards or other integrated circuit mounting substrates, the integrated circuits generally are mounted parallel to and facing the printed circuit board such that a face of the integrated circuit is adjacent a face of the printed circuit board. This packaging technology can allow a large number of input/output connections to be provided between the integrated circuits and the printed circuit board, especially when solder bump technology is used, which can cover the entire face of the integrated circuits with solder bump connections. Unfortunately however, this packaging technology may limit the packaging density, because the large faces of the integrated circuit chips are mounted adjacent the face of the printed circuit board. Moreover, this packaging technology may limit the speed of the integrated circuits due to the relatively long interconnection lines on the printed circuit board.
In order to increase the packaging density of chips on the printed circuit board, three-dimensional packaging technologies also have been proposed, wherein the chips are mounted orthogonal to the circuit board so that a chip edge is adjacent the face of the circuit board. See for example U.S. Pat. No. 4,266,282 to Henle, et al. entitled Vertical Semiconductor Integrated Circuit Chip Packaging; U.S. Pat. No. 5,347,428 to Carson, et al. entitled Module Comprising IC Memory Stack Dedicated to and Structurally Combined with an IC Microprocessor Chip and U.S. Pat. No. 5,432,729 to Carson, et al. entitled Electronic Module Comprising a Stack of IC Chips Each Interacting with an IC Chip Secured to the Stack. In these patents, solder bump technology is used to connect the edges, rather than the faces, of integrated circuit chips to a substrate. Unfortunately, an edge-to-face connection may be difficult and/or costly to produce.
Moreover, in using solder bump technology to interconnect a three-dimensional package, it may be difficult to fabricate the solder bump to bridge from one substrate to another. In particular, it may be difficult to form solder that extends beyond the edge of a chip because the chip sawing or dicing operation may remove or damage the solder that extends beyond the chip edge. Moreover, during solder reflow, it is well known that the solder takes the shape of a hemisphere or partial hemisphere on a contact pad. Thus, it may be difficult to cause the solder on one contact pad to extend onto another contact pad, in a three-dimensional package. Even if solder is placed on pair of adjacent contact pads in a three-dimensional package, it may be difficult to cause the reflowed solder to join up, rather than forming individual solder bumps.
A major advance in three-dimensional microelectronic packaging that uses solder bump technology to interconnect a three-dimensional package is described in U.S. Pat. No. 5,793,116 to the present inventor Rinne, et al. entitled Microelectronic Packaging Using Arched Solder Columns, the disclosure of which is hereby incorporated herein by reference in its entirety. As described therein, a microelectronic package may be formed in which solder bumps on one substrate are expanded, to thereby extend to and contact a second substrate and thereby form a solder connection. In particular, a first microelectronic substrate is oriented relative to a second microelectronic substrate, such than an edge of the second microelectronic substrate is adjacent the first microelectronic substrate. One of the first and second microelectronic substrates includes a plurality of solder bumps thereon, adjacent the edge of the second microelectronic substrate. The plurality of solder bumps are expanded to extend to and contact the other of the first and second microelectronic substrates.
In the above-cited Rinne et al. '116 patent, the plurality of solder bumps may be expanded by reflowing additional solder from an elongated, narrow solder-containing region adjacent the solder bump. into the solder bump. This region also may be referred to as a solder reservoir. Surface tension from the elongated solder-containing region can cause the solder to flow from the elongated solder-containing region into the solder bump, thereby expanding the volume of the solder bump and causing it to extend to and contact the other substrate. The plurality of solder bumps may be formed on the second microelectronic substrate adjacent the edge thereof. The solder bumps are caused to extend laterally beyond the edge of the second microelectronic substrate, to thereby contact the first microelectronic substrate. The solder bumps may be caused to extend laterally by reflowing additional solder into the plurality of solder bumps from the elongated, solder region adjacent the solder bump. Accordingly, solder bumps may be caused to bridge a gap to extend onto and contact an adjacent pad.
This breakthrough technology also is described in U.S. Pat. No. 5,892,179 to the present inventor Rinne, et al. entitled Solder Bumps and Structures for Integrated Redistribution Routing Conductors; U.S. Pat. No. 5,963,793 to the present inventor Rinne, et al. entitled Microelectronic Packaging Using Arched Solder Columns and U.S. Pat. No. 5,990,472 to the present inventor Rinne entitled Microelectronic Radiation Detectors for Detecting and Emitting Radiation Signals. The disclosures of all of these patents are hereby incorporated herein by reference in their entirety.
SUMMARY OF THE INVENTION
Microelectronic packages according to embodiments of the present invention include a first microelectronic substrate, a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate, and a plurality of first solder bumps between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate, that connect (electrically and/or mechanically) the second microelectronic substrate to the first microelectronic substrate and that are confined to within the edge of the second microelectronic substrate. The edge of the second microelectronic substrate is adjacent the vertex of the acute angle.
In other embodiments, a third microelectronic substrate also may be provided on the first microelectronic substrate that laterally overlaps the second microelectronic substrate. A plurality of second solder bumps connect the third microelectronic substrate to the first microelectronic substrate. In some embodiments, the second and third microelectronic substrates are oriented parallel to one another at the acute angle relative to the first microelectronic substrate. In other embodiments, the plurality of second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, wherein the second edge of the third microelectronic substrate is adjacent the vertex and wherein the first edge of the third microelectronic substrate is opposite the vertex.
Embodiments of the present invention stem from a realization that if integrated circuits are mounted on a printed circuit board at an acute angle rather than perpendicular thereto, the acute angle may be limited so that the solder bumps can bridge from the integrated circuit to the printed circuit board without the need to expand the solder bumps during reflow. Accordingly, solder reservoirs. which can be difficult and/or costly to produce, need not be used for three-dimensional packaging. Moreover, by allowing multiple integrated circuit dies to laterally overlap on the printed circuit board, an increase in packaging density and/or reduced signal path lengths can be obtained compared to conventional mounting of integrated circuits on printed circuit boards. In particular, integrated c
Gandhi Jayprakash N.
Lindinger Michael L.
Myers Bigel & Sibley & Sajovec
Unitive Electronics Inc.
LandOfFree
Microelectronic packages in which second microelectronic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microelectronic packages in which second microelectronic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microelectronic packages in which second microelectronic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2879658