Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2000-01-31
2002-07-16
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S239000
Reexamination Certificate
active
06420738
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electric charge detector suitable for a solid-state image device. Particularly, the present invention relates to an electric charge detector that can reduce distributed noises to improve the SNR (Signal-to-Noise Ratio).
Conventionally, the solid-state image devices such as CCD solid-state image devices utilizing the charge transfer function include electric charge detectors respectively. The common floating diode amplifier-type electric charge detector is disclosed in, for example, the reference “SOLID-STATE IMAGE DEVICES”, authored by Yuji KIUCHI, supervised under Shin HASEGAWA, published by SHOKODO Publishing Co., and compiled by the Institute of Television Engineers of Japan (First Edition issued on Jul. 30, 1986), (see line 5, page 74 to line 5, page 75 and FIGS. 3.26(
a
) and 3.26(
b
)).
FIG. 7
is a plan view schematically illustrating the configuration of a conventional electric charge detector.
FIG. 8
is a cross sectional view illustrating the configuration of the conventional electric charge detector, taken along the line D—D of FIG.
7
.
In the conventional electric charge detector, a P-type well region
29
is formed on the N-type semiconductor substrate
30
. The P-type well region
29
is grounded. An N-type well region
22
is selectively formed on the P-well region
29
. A LOCOS (local oxidation) structure (not shown), for instance, is formed around the N-type well region
22
. Heavily-doped N-type diffused layers
26
and
28
are formed on the surface of the N-type well region
22
.
A metal conductor (wire)
25
is in ohmic-contact with the heavily-doped N-type diffused layer
26
. A source-follower amplifier
24
acting as an output amplifier is selectively connected to the metal conductor
25
. An output circuit
24
a
is connected to the source follower amplifier
24
to receive the output signal VOUT.
An input gate electrode
21
is formed on the N-type well region
22
via the insulation film such as thermally-grown silicon dioxide film (not shown). The input gate electrode
21
controls the signal charge flown from an adjacent charge-coupled device (not shown). A gate terminal
21
a
is connected to the input gate electrode
21
to receive the gate electrode VOC.
A control terminal
28
a
is in connect with the surface of the heavily-doped N-type diffused layer
28
to reset potential VRD.
A gate electrode
27
is formed over the N-type well region
22
between the heavily-doped N-type diffused layers
26
and
28
via the insulation film (not shown) such as thermally-grown silicon dioxide. A gate terminal
27
a
is connected to the gate electrode
27
to receive the gate voltage &phgr;R.
In the conventional electric charge detector, a floating PN-junction diode
23
is formed of the P-type well region
29
, the N-type well region
22
, and the heavily-doped N-type diffused layer
26
, which are disposed between the input gate electrode
21
and the input gate electrode
27
. Moreover, a MOSFET-type reset transistor has the heavily-doped N-type diffused layer
26
acting as a source, the gate electrode
27
acting as a gate, and the heavily-doped N-type diffused layer
28
acting as a drain.
FIG. 9
is a timing chart illustrating the operation of the conventional electric charge detector. In the conventional electric charge detector, when the gate electrode
27
is set to a high level, the MOSFET-type reset transistor will be turned on, so that unwanted signal charges accumulated in the floating diode
23
is drawn to the heavily-doped N-type diffused region
28
acting as the drain thereof. At the same time, the surface potential of the floating diode
23
is held to a fixed reset potential VRD of about 12 to 15 volts.
Thereafter, when the gate electrode
27
is set to a low level, the reset transistor is turned off. In the charge-coupled device, the signal charge Q (that is, the signal current I (nA)) passes underneath the input gate electrode
21
and then sinks into the potential well of the floating diode
23
. The signal charge Q is expressed by the following formula (1).
Q=∫Idt (1)
The source follower amplifier
24
outputs as an output signal VOUT the resulting variation of the channel potential of the floating diode
23
via the metal conductor
25
. That is, the signal charge Q (expressed by the formula (1)) is converted into a variation in the surface potential of the floating diode
23
. The source follower amplifier
24
amplifies the variation via the metal conductor
25
and then outputs it as a signal voltage.
When the output signal VOUT is output, the electric charge accumulated in the floating diode
23
are unwanted. This boosts the gate electrode
27
to a high level to reset the reset transistor
24
. As a result, the unwanted charges are drawn out. The electric charges transferred from the charge-coupled device are sequentially detected by repeating the series of the operation, so that a predetermined voltage is obtained.
However, in the conventional electric charge detector, thermal noises and distributed noises generate because of the switching operation of the reset transistor in the reset operation, thus deteriorating the S/N ratio.
Those noises do not depend on the signal charge amount accumulated in the floating diode. Hence, this problem becomes remarkable as the integration density of the solid-state image device increases, that is, with shrinkage of the unit pixel size and reduction of a signal charge amount per pixel.
It is known that the thermal noise is proportional to the absolute temperature or the junction capacity of the floating diode. The floating diode is designed to reduce its size as small as possible, within an allowable range of the normal design rule.
The principle on the generation of distributed noises is disclosed in, for instance, “Partition Noise in CCD Signal Detection”, written by N. Teranishi and N. Mutoh, IEEE Trans, Electron devices, Vol. ED-33, pp. 1696-1701(1986).
Each of
FIGS. 10
to
12
is a schematic diagram illustrating the principle on generation of distributed noises according to steps. As shown in
FIG. 10
, the floating diode
23
accumulates electric charges. When the reset transistor is in an off state, the signal charges Q and electrons exist in the potential well of the floating diode
23
.
Thereafter, as shown in
FIG. 11
, when the potential of the gate electrode
27
is in a high level and when the reset transistor is in an on state, the signal charge Q is drawn out of the potential well through the heavily-doped N-type diffused layer
28
acting as the drain of the reset transistor. In this case, electrons exist underneath the gate electrode
27
because the potential VRD of the reset channel underneath the gate electrode
27
is lower than that of the heavily-doped N-type diffused layer
28
.
With the potential of the gate electrode
27
in a low level and with the reset transistor in an off state, as shown in
FIG. 12
, part of electrons existing in the reset channel are distributed to the floating diode. This causes the distributed noise. It is known that the charge amount q of the distributed noise is proportional to the reset channel capacity and the absolute temperature.
In consideration of variations in the channel potential of the reset transistor due to the device fabrication, the channel potential underneath the gate electrode
27
of the reset transistor is normally about 0.5 volts higher than the reset drain potential VRD at the on state.
The capacitance C
1
of the reset channel is normally about ¼ to ⅕ of that of the floating diode CO. Hence, the following formula (2) is applicable to the voltage conversion value Np of the distributed noise.
C
0
×Np=C
1
×0.5×K
C
1
=(¼)C
0
~(⅕)C
0
(2)
where K is a ratio of electrons underneath the reset channel to be distributed to the floating diode
23
and is 0≦K≦1.
Therefore, the voltage conversion value Np of the distributed noise is expressed by the followin
Foley & Lardner
NEC Corporation
Ngo Ngan V.
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