Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-12-15

2002-03-05

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233100, C365S189050

Reexamination Certificate

active

06353572

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for latching address signals in a semiconductor integrated circuit having memory cells.
2. Description of the Related Art
With the development of semiconductor manufacturing technology, a semiconductor integrated circuit has been increasing its operating speed. In particular, microcomputers and the like has been improving in operating frequency year by year, which increases disparity from the operating frequencies of semiconductor memories such as DRAMs.
To narrow this disparity, there have been developed high speed DRAMs including SDRAMs (Synchronous DRAMs) and DDR SDRAMs (Double Data Rate Synchronous DRAMs). SDRAMs perform data transfer from/to exterior in serial, and read/write data from/to memory cells in parallel so as to improve data transmission speed.
Nevertheless, a data bus usage rate decreases during random accesses when the SDRAMs perform read operations and write operations in combination. A drop in data bus usage rate lowers the transmission amount of data per unit time. On this account, it has been difficult for high speed DRAMs such as SDRAMs to be used as, for example, graphics memories which perform frequent random accesses such as image processing.
In the meantime, for the sake of improvement in data bus usage rate, there have recently been proposed SDRAMs having a function called “delayed write”, in which write data supplied in correspondence with a write command is written to memory cells at the time of supplying the next write command.
FIG. 1
shows the operation of a DDR-SDRAM having a delayed write function. In this example, the number of clock cycles from the acceptance of a read command to the output of read data, or a read latency, is set at “2”. The number of clock cycles from the acceptance of a write command to the output of write data, or a write latency, is also set at “2”.
Initially, in synchronization with a clock signal CLK, read commands RD
0
, RD
1
and read addresses ADR
0
, ADR
1
are successively supplied as a command signal CMD and an address signal ADD, respectively, so that a memory core operates (
FIG. 1
, (
a
)). Then, two clocks after the acceptance of the individual read commands RD
0
and RD
1
, read data Q
00
, Q
01
, Q
10
, and Q
11
are output in succession as a data signal DQ (
FIG. 1
, (
b
)).
Next, two clocks after the acceptance of the read command RD
1
, a write command WR
0
and a write address ADW
0
are supplied (
FIG. 1
, (
c
)). The write address ADW
0
is held in an address resister temporarily. Here, in synchronization with the write command WR
0
, previous write data held in a data resister is written to the memory core by using a previous write address held in the address register (
FIG. 1
, (
d
)).
Write data DA
0
and DA
1
are supplied two clocks after the write command WR
0
. That is, the write data DA
0
and DA
1
are supplied in synchronization with the clock signal CLK after the output of the read data Q
11
(
FIG. 1
, (
e
)). The write data DA
0
and DA
1
are held in the data resister temporarily (
FIG. 1
, (
f
)).
Then, in synchronization with the clock signal CLK subsequent to the write command WR
0
, read commands RD
2
, RD
3
, and RD
4
are supplied in succession, and read operations are carried out (
FIG. 1
, (
g
)).
Moreover, two clocks after the acceptance of the read command RD
4
, a next write command WR
1
and write address ADW
1
are supplied (
FIG. 1
, (
h
)). Input/output circuits and the memory core operate in synchronization with the write command WR
1
, whereby the write data DA
0
and DA
1
held in the data register are written to the memory core by using the previous write address signal ADW
0
held in the address register (
FIG. 1
, (
i
)).
Next, write data DA
2
and DA
3
are supplied two clocks after the write command WR
1
. The contents of the data register are rewritten by the write data DA
2
and DA
3
(
FIG. 1
, (
j
)).
As described above, in an SDRAM having a delayed write function, write operations on memory cells are performed at different timing from the accepting timing of write data. This avoids a conflict between the operation of the memory core corresponding to a write command and the operation of the memory core unit corresponding to a read command supplied immediately after the write command. As a result, the data bus usage rate improves as compared to those of ordinary SDRAMs and the amount of data transfer increases. In other words, high speed operations are enabled.
FIG. 2
shows an address latching circuit
1
in the SDRAM having a delayed write function.
This address latching circuit
1
selects either a read address signal RADD supplied from exterior or a write address signal WADD supplied from the address register mentioned above, and outputs the same to an address decoder (not shown).
The address latching circuit
1
has a switching circuit
2
for transmitting the read address RADD, a switching circuit
3
for transmitting the write address WADD, a latch
4
consisting of two inverters, and an inverter
5
. The switching circuits
2
and
3
consist of a CMOS transmission gate and an inverter for controlling the pMOS transistor (hereinafter simply referred to as pMOS) in this transmission gate. The switching circuit
2
is controlled by a read clock signal RCLK which is activated in read operations. The switching circuit
3
is controlled by a write clock signal WCLK which is activated in write operations. The latch
4
outputs an internal address signal ADDCX and, through the inverter
5
, an internal address signal ADDCZ.
FIG. 3
shows an example of the operation of the address latching circuit
1
. Parenthetically, in the following description, some signal names will be referred to in abbreviations such as “RADD signal” for “read address signal RADD”.
Initially, the RADD signal is supplied to the address latching circuit
1
in a high-level period of the RCLK signal (
FIG. 3
, (
a
)). Here, in order to avoid a mislatch, the RADD signal is supplied throughout the high-level period of the RCLK signal. That is, the RADD signal need be supplied to satisfy both a setup time tS for a rising edge of the RCLK signal and a hold time tH for a falling edge of the same. The RADD signal is latched into the latch
4
, and output as complementary ADDCZ and ADDCX signals (
FIG. 3
, (
b
)).
Moreover, the WADD signal is supplied to the address latching circuit
1
throughout a high-level period of the WCLK signal (
FIG. 3
, (
c
)). Likewise, the WADD signal also requires the setup time tS and the hold time tH. The WADD signal is latched into the latch
4
and is output as complementary ADDCZ and ADDCX signals (
FIG. 3
, (
d
)).
Now, description will be given of the malfunctions of the address latching circuit
1
.
For example, when the RADD signal is changed during a high-level period of the RCLK signal (
FIG. 3
, (
e
)), it is impossible for the latch
4
to correctly latch the RADD signal (low level, here) (
FIG. 3
, (
f
)). When a hazard arises on the RCLK signal during the latching period of the WADD signal (
FIG. 3
, (
g
)), it is also impossible to correctly latch the WADD signal (low level, here) (
FIG. 3
, (
h
)). Therefore, an incorrect address signal is supplied to the address decoder. As a result, the memory core receives a correct address signal to start operating, and then receives a different address during the operation, which leads to malfunction. Furthermore, when both the RCLK signal and the WCLK signal are activated simultaneously as shown in FIG.
3
(
g
), a feedthrough current flows due to the conflict between the RADD signal and the WADD signal.
FIG. 4
shows another address latching circuit
6
.
This address latching circuit
6
includes a resetting circuit
7
which receives a latch address signal ADDL output from the latch
4
and outputs the address signals ADDCZ and ADDCX. The resetting circuit
7
has NAND gates
7
a
and
7
b
to be controlled by a reset signal RESETX. The resetting circui

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