Signal conversion circuit for stable differential...

Details Signal conversion circuit for stable differential... Signal conversion circuit for stable differential...

2001-01-16

2002-08-06

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S252000, C330S253000, C330S261000

Reexamination Certificate

active

06429743

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal level conversion circuit and, more specifically, to a signal level conversion circuit for performing a differential operation and a semiconductor device provided with the same as an input buffer.
2. Description of the Background Art
Generally, a semiconductor device such as a memory device is provided with an input buffer generating an internal signal in accordance with an externally applied input signal. The input buffer converts the potential level of the external signal in a specific range to fall within a range suitable for the internal operation of the semiconductor device.
In this case, the level of the internal signal is set based on a correlationship between the potential of the external signal and a reference potential. If, for example, L and H level potentials of the internal signal are respectively Vss and Vdd, the reference potential is determined as (Vdd+Vss)/2, and the potential of the external signal is compared with the reference potential for setting the level of the internal signal.
In a semiconductor device such as a DDR (Double Data Rate)-SDRAM (Synchronous Dynamic Random Access Memory), which operates in response to both activation and inactivation edges of an external clock EXT.CLK used as a reference, external clock EXT.CLK and its inverted clock /EXT.CLK are input and an internal clock signal is generated based on a correlationship between the potential levels of external clock signal EXT.CLK and inverted clock /EXT.CLK using inversion clock /EXT.CLK as a reference.
The generation of the internal signal at the input buffer is accompanied by a delay required for converting a correlationship between the potentials of the external and reference signals (potential difference) to the level of the internal signal. Thus, at the input buffer, as the potential levels of the input external signal and reference signal vary, the delay caused by the generation of the internal signal also varies. In a high speed device such as the above mentioned DDR-SDRAM, the timing of an output signal must be strictly adjusted with respect to the timing of an input signal, and therefore variation in delay of the internal signal at the input buffer cannot be ignored. In view of the above, an input buffer which is less affected by variation in the potential level of an input external signal is required.
FIG. 9
is a circuit diagram showing a structure of a general differential input buffer
300
used for a semiconductor device.
Referring to
FIG. 9
, input buffer
300
receives an external signal such as an external clock EXT.CLK and a reference signal Vr, and differentially amplifies the potential difference thereof for generating an internal clock INT.CLK of an internal signal. H and L level potentials of the internal signal are respectively a power supply potential Vdd and a ground potential Vss. Reference signal Vr is for example an inverted clock /EXT.CLK of external clock EXT.CLK or a constant direct current potential VREF at a level intermediate between power supply potential Vdd and ground potential Vss.
Input buffer
300
includes P type MOS transistors QP
1
and QP
2
respectively arranged between power supply potential Vdd and nodes Na, Nb; and N type MOS transistors QN
1
and QN
2
respectively arranged between a common node Nc and nodes Na, Nb. Transistors QP
1
and QP
2
have their gates connected to node Na. Transistors QN
1
and QN
2
have their gates respectively receiving a reference signal Vr and an external signal.
Input buffer
300
further includes an N type MOS transistor QNc electrically connected between common node Nc and ground potential Vss and having its gate receiving a constant direct current potential Vmn. Direct current potential Vmn is set at an intermediate potential level higher than a threshold value of transistor QNc. Thus, transistor QNc serves as a constant current source and supplies an operation current for differential amplification.
Transistors QN
1
, QN
2
, QP
1
, QP
2
, and QNc form a so-called current mirror amplifier.
If the gate potentials of transistors QN
1
and QN
2
are the same, currents i
1
and i
2
flowing through these transistors remain unchanged, having a value half a current i
0
flowing through transistor QNc. Then, the potential level at node Nb generating the internal signal converges to a level where currents flowing through transistors QP
1
and QP
2
serving as a load equal to currents flowing through transistors QN
1
and QN
2
.
Even if the gate potentials of transistors QN
1
and QN
2
vary, as long as the potentials thereof are the same, i.e., there is no potential difference, currents i
1
and i
2
have the same value, i.e., half current i
0
. Thus, the potential level at node Nb remains constant. Accordingly, when the external signal and reference signal change in the same manner, the internal operation of the input buffer would not be affected by variation in external potential level. In other words, a delay caused by the generation of the internal signal remains constant.
If the gate potential of transistor QN
2
, i.e., the potential of the external signal, increases to a level slightly above the gate potential of transistor QN
1
, i.e., the potential of the reference signal, current i
2
flowing through transistor QN
2
increases and current i
1
flowing through transistor QN
1
correspondingly decreases. On the other hand, since current i
0
flowing through the circuit as a whole remains unchanged, the potential level at node Nb decreases in accordance with magnitudes of increase in current i
2
of transistor QN
2
and a load.
Conversely, if the gate potential of transistor QN
2
decreases to a level slightly below the gate potential of transistor QN
1
, current i
2
flowing through transistor QN
2
decreases but current i
1
flowing through transistor QN
1
increases. Since current i
0
flowing through the circuit as a whole remains unchanged, in this case, the potential level of internal node Nb increases in accordance with magnitudes of decrease in current i
2
of transistor QN
2
and a load. Thus, the internal signal generated at node Nb amplifies the gate potential difference between transistors QN
1
and QN
2
, but does not affect in-phase component or direct current component.
However, to achieve stable operation of differential input buffer
300
with a high voltage gain, transistors QN
1
, QN
2
, QP
1
, QP
2
, and QNc, forming a current mirror amplifier, must operate in a saturation region.
Particularly, current supply transistor QNc serves as a constant current source through operation in the saturation region. To allow operation of current supply transistor QNc in the saturation region, the drain potential thereof, i.e., the potential level at common node Nc must equal Vmn−Vth (Vth: threshold voltage of transistor QNc). Generally, the potential level at common node Nc must be about several hundreds of mili-volts to assure operation current for a differential operation.
Further, the operation of transistor QN
2
in the saturation region requires that the gate potential of transistor QN
2
, i.e., the potential of the external signal, must be at least a level higher by Vth′ (Vth′: a threshold voltage of transistor QN
2
) than the potential level at common node Nc. Assume that Vth is about 0.7V, as in a usual case. To ensure that transistor QN
2
always operates in the saturation region, the gate potential must be at least about 1.0V regardless of the level of the external signal.
Recently, driving potentials and signal amplitude levels of interface systems have been on the decrease along with power supply potentials for the purpose of reducing power consumption. Thus, at a lower limit of a specified range of potential level, the gate potential of transistor QN
2
cannot attain a sufficient level. As a result, a stable differential amplification operation cannot be achieved by input buffer
300
.
In an SSTL
2
(Stub Series Terminated Logic for 2.5V) as one of typical interface standa

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