Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-08-29
2002-03-26
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185240, C365S185290, C365S185300, C365S185330
Reexamination Certificate
active
06363013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to floating gate memory devices, including but not limited to devices such as flash EPROM, EEPROM, and the like. In particular the present invention relates to methods and circuits for converging the low threshold voltages of the several cells of the memory array into an acceptable range of values for such voltages, and for precluding the over soft-programming of these memory devices.
2. Description of Related Art
Non-volatile floating gate memory devices based on integrated circuit technology are important elements of many computer, communication, and consumer products. There currently exist several classes of non-volatile memory devices based on arrays of floating gate memory transistors, which devices are both programmable and erasable. These devices include, but are specifically not limited to flash EPROMs, and EEPROMs. Flash memory devices may be based on either EPROM or EEPROM technology.
A conventional flash EPROM memory array generally uses a single transistor with stacked polysilicon gates for each cell within the array. The transistor is typically formed on a p-type well, and has an n-type source and drain regions provided within the well. The transistors can be selectively charged or programmed, and typically hold their program charge for an extended period of time, thereby holding the information stored thereon in a non-volatile fashion.
Programming a flash EPROM cell generally involves injecting the floating gate of one or more selected cells in the array with channel hot electrons, thereby accumulating a net negative charge on the cell's floating gate. This “hot electron injection” is typically accomplished by simultaneously placing a positive voltage on both the control gate and drain of the cell. Injecting these electrons places a net negative charge upon the floating gate, thereby increasing the turn-on threshold of the memory cell. With this higher threshold, the cell is in a non-conductive state when addressed with a read voltage applied to the cell's control gate.
When erasure of one or more cells in a flash EPROM device is required, the negative charge in the floating gate of each cell is drained off, thereby lowering the turn-on threshold of the cell. With this lower threshold, the cell turns on to a conductive state when addressed with a read voltage applied to the control gate of the cell.
Conventional flash EEPROM memory arrays for low power applications use a low current charge transfer mechanism called channel Fowler-Nordheim (F-N) tunneling to increase electrons at the floating gate, thereby raising the threshold voltage V
T
, and programming the cell. In this programming mechanism, charge is added to the floating gate of the memory cell through a thin layer of tunnel oxide. To erase one or more cells, these devices utilize bit line, or drain side F-N tunneling to discharge electrons from the floating gates thereof to lower the cell's low threshold voltage. In this erasure mechanism, charge is removed from the floating gate through the tunnel oxide layer. This methodology enables the simultaneous erasing and programming of different cells within the same page. It should be noted that the word “page” is defined herein as a certain number of cells within a common word line.
From the preceding discussion, it may be inferred that for a given memory storage device there is an optimal low threshold voltage, or range of low threshold voltages, which define the erased state for a given cell. This is indeed the case. It is also a fact however, that several factors can serve to move the low threshold voltage of a given cell out of the acceptable range for its desired state.
A first problem, which can occur during the erase operation, is that of over-erasure. Over-erasure occurs if too many electrons are removed from the floating gate, leaving the gate with a threshold voltage which is too low. This very low threshold voltage, defined as either negative, zero, or only slightly positive, biases the memory cell slightly on, so that a small current can leak through the memory, even when the cell is not addressed, thereby causing a false reading. Thus, an over-erased cell can cause a false reading due to its leakage current.
A second problem is that over-erasure not only causes the previously discussed false readings, but it can render more difficult the successful re-programming of cells, especially for channel hot electron programming. This additional problem eventuates because the number of electrons, or net charge, required to change an over-erased cell to the programmed state is larger than for normal cells. Accordingly, a charge normally sufficient to program a cell may not raise the over-erased cell's threshold voltage high enough to reliably program the cell.
A third problem is that the design of conventional flash EEPROMs often utilizes a double implant at the drain side to reduce band-to-band stress. The shallower source side junctions within such a cell are also known to enhance a secondary hot electron injection, which enhances soft programmability. Cell reliability would be degraded where electron injection and discharge are contemporaneously conducted in the same region of the array, that is to say, drain side in flash EEPROMs, and the soft program efficiency of the deeper double implant drain side is also lower than that of shallower source side.
Finally, because F-N tunneling can produce an abnormal discharge behavior for some cells, particularly where electron injection and discharge are simultaneously conducted in close proximity, the range of threshold voltages for several of the cells in the array can fall out of design bounds. In other words, it is possible that F-N tunneling may cause one or more abnormal cells in a page to have an ultra-low threshold voltage while other cells in the page are at the high end of the low threshold range, or may even exceed the high end of this range. This wide divergence can affect the reliability of the several cells within the array, as previously discussed.
Because both the erase and program operations can affect different cells within a single array in different manners, floating gate memory designs often include circuitry for verifying the success of the erase and program steps. One such device is taught in U.S. Pat. No. 4,875,118. In accordance with the principles enumerated in this reference, if an array does not pass an erase-verify step the entire array is usually re-erased. Where one or more cells have been so over-erased as to lower the threshold voltage below the normal range, some of these re-erase methodologies actually aggravate the already the over-erased cells in the array.
U.S. Pat. No. 5,414,664 teaches one solution to this over-erase problem associated with prior erase verification processes. The invention taught therein teaches a method wherein only those blocks in a memory array which have failed the erase verify operation are re-erased. This then precludes the re-erase of the entire array after each verify operation, thereby mitigating the over-erase phenomenon. Although the methodology taught in this reference mitigates the problem it does not solve it entirely, as cells which have been over-erased are not repaired following the over-erasure. Accordingly, a repair process was needed which actually corrects over-erased cells.
One such repair process, disclosed in U.S. Pat. No. 5,233,562, teaches a methodology for effecting such a repair using so-called drain disturb, source disturb, or gate disturb techniques. After each repair performed by the process taught in this reference, a time-consuming repair verification operation of the entire array is required. In order to perform these repair and repair verification processes in a more time efficient manner, further improvements were required.
A methodology which improves the timeliness of repairs to over-erased cells in flash memory and other floating gate memory devices is taught in U.S. Pat. No. 5,745,410, herewith incorporated by reference. T
Chen Ming-Shang
Lin Baw-Chyuan
Lo Ying-Che
Lu Wenpin
Su Chun-Lien
Beyer Weaver & Thomas LLP.
Lam David
Macronix International Co. Ltd.
Nelms David
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