Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-06-29
2002-09-24
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230060, C365S189080
Reexamination Certificate
active
06456558
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
This application claims priority from Korean Application entitled “Column Decoding Apparatus for Use in a Semiconductor Memory Device”, Application No. 2000-37321, filed on Jun. 30, 2000 and incorporates by references its disclosure for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a column decoding apparatus in a semiconductor memory device, and, more particularly, to a column decoding apparatus enabling a column selecting signal only within a selected block.
2. Prior Art of the Invention
FIG. 1
is a diagram showing the configuration of a typical memory cell array of a semiconductor memory device, and
FIG. 2
is a diagram of a conventional column decoding apparatus.
The semiconductor memory device shown in
FIG. 1
comprises a plurality, e.g., 16 or 32, of memory cell array blocks; a plurality of block controlling units, each for selecting a corresponding one of the memory cell array blocks;, a plurality of bit line sense amplifier (BLSA) arrays, each for reading/writing of the memory cell; and a column decoder (Y-DEC).
FIG. 2
is a block diagram of a conventional column decoding apparatus of the device of FIG.
1
.
FIG. 2
shows the output of the column decoder (Y-DEC) as a column selecting signal (YI). Since YI is connected to the column selecting transistors (i.e., driving transistors) for all the blocks, the transistor load of the column decoder is very large (i.e. “heavy”).
FIG. 3
shows a timing diagram of the conventional column decoding apparatus of FIG.
2
. When, for example, there are 16 memory cell array blocks, the transistor load of one column selecting signal YI is 68 (4 column selecting transistors×17 BLSA array). Therefore, the rise time/fall time of the column selecting signal increases to detrimentally increase memory access time. In addition, because column selecting signal YI operates as a pulse, the column selecting signal YI in a memory, which operates in high frequency range, is degraded so that reading/writing in the memory cannot be accurately executed.
SUMMARY OF THE INVENTION
The present invention provides, in a semiconductor memory device, a column decoding apparatus capable of improving the rise/fall time of a column selecting signal by reducing the transistor load associated with the column decoder by enabling the column selecting signal of a selected block.
In accordance with one aspect of the present invention, there is provided, in a semiconductor memory device having a plurality of memory cell arrays, bit line sense amplifier arrays and block controlling units, a column decoder and column selecting transistors formed between the plurality of bit line sense amplifier arrays, and a data line. The column decoding apparatus comprising: column selecting signal generating units, each receiving a control signal from the block controlling units and an output signal from the column decoder for generating a column selecting signal activated only within a selected block, to drive the column selecting transistors.
REFERENCES:
patent: 4926384 (1990-05-01), Roy
patent: 5499218 (1996-03-01), Ahn et al.
patent: 5650977 (1997-07-01), Kyung et al.
patent: 5923607 (1999-07-01), Suh
patent: 6327215 (2001-12-01), Ternullo, Jr. et al.
Hynix / Semiconductor Inc.
Phan Trong
Townsend and Townsend / and Crew LLP
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