Method of forming integrated interconnect for very high density

Details Method of forming integrated interconnect for very high density Method of forming integrated interconnect for very high density

1993-12-02

1995-02-14

Fourson, George

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

053895592

ABSTRACT:
A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.

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