Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
1999-12-06
2002-01-22
Rosasco, S. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C716S030000
Reexamination Certificate
active
06340542
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, a photomask, and a master mask. More particularly, the invention relates to a method of transferring the pattern of a master mask to a substrate or a photomask by means of a projection-type exposure apparatus.
FIG. 1
shows the sequence of manufacturing a conventional logic device. More precisely,
FIG. 1
shows the sequence of designing and manufacturing a system LSI. At first, the design specification is prepared in Step
111
in accordance with requests made by the customer. In Step
112
, a Register Transfer Level (RTL), which is a kind of a Hardware Description Language (HDL), is prepared on the basis of the design specification. In Steps
113
and
114
, the RTL is converted to a circuit diagram by using a logic synthesis tool. In Steps
115
and
116
, a Placement and Routing (P&R) tool is used, thereby preparing a layout diagram.
The layout of function blocks, known as standard cells, macro cells, and IP blocks, is designed for the layers located below the wiring layer. Then, the data representing this layout is generated in the form of an information library. In accordance with the information library, the cells corresponding to the function blocks of circuit diagrams are automatically arranged by the placement and routing function of the P&R tool. In the wiring layer, cells are arranged to work in compliance with cells arranged in lower layers. These cells are automatically prepared by using the placement and routing function in accordance with the circuit diagrams.
A one-chip LSI layout diagram is thus prepared. In Step
117
, the LSI layout diagram is subjected to Process Proximity Correction (PPC), which is performed by using data conversion software, and is then converted to mask-writing data.
The components of the pattern may be made smaller, approaching the minimum size equivalent to the resolution of the exposure apparatus used. If so, each pattern component on the wafer will have its corners rounded during photolithography due to the optical proximity effect (OPE). Consequently, the pattern formed may not correlate to the desired pattern. For example, the end portions of each pattern component may become shorter than is designed. To make matters worse, the widths of pattern components may change in some cases due to micro-loading effect, after the mask layer or the wafer has been etched. The optical proximity effect and the micro-loading effect are generally called “PPE (Process Proximity Effect).” The technique of correcting the deformation of a pattern, caused by PPE, is known as “PPC.”
In Step
118
, a mask-writing tool draws a pattern on a substrate in accordance with the mask-writing data, thereby manufacturing a master mask. In Step
119
, an exposure apparatus applies light to a wafer through the master mask. An LSI pattern is thereby formed on the wafer in Step
120
.
As the integration density of an LSI pattern increases, the components of device patterns must have smaller sizes of higher precision. It is therefore necessary to form a larger master mask for each device pattern. Therefore, one master mask cannot alone represent the entire one-chip LSI pattern. That is, two or more master masks must be formed to represent a one-chip LSI pattern.
FIG. 2
is a flow chart explaining a conventional method of manufacturing a semiconductor device, in which a plurality of master masks are used to form a one-chip LSI pattern. As shown in
FIG. 2
, the actual layout diagram of an LSI is prepared in Step
206
. In Step
207
, the layout diagram of the LSI pattern is converted to data, and the resultant data is divided into parts by the use of a chip-data cutting tool. The parts of the data thus provided will be used to prepare master masks that form a one-chip LSI pattern. The flow chart of
FIG. 2
, explaining the method of manufacturing an LSI, is basically the same as the flow chart of
FIG. 1
but different in that the data representing the layout of the LSI is divided into, for example, two parts by using a chip-data cutting tool.
FIGS. 3A and 3B
are diagrams for explaining, in detail, a conventional method of manufacturing a semiconductor device.
Two master masks
131
and
132
are prepared on the basis of two pattern data items, respectively. Light is applied to a wafer
4
through first master mask
131
. Shaded regions
133
of wafer
4
are thereby exposed to light as is illustrated in FIG.
3
A. Next, light is applied to wafer
4
through the second master mask
132
, whereby shaded regions
134
of wafer
4
are exposed to light as is shown in
FIG. 3B. A
product
1
is thereby made. Since the chip has been divided along a center line into two parts, the cell B is divided into two parts B′ and B″, and the cell D into two parts D′ and D″, as is illustrated in
FIGS. 3A and 3B
. Inevitably, the pattern in the cell B is cut into two parts, and the pattern in the cell D into two parts. Four butting portions of the pattern are therefore formed on the wafer
4
. As shown in
FIG. 3B
, pattern components
135
(e.g., resist strips) on one part may not align with pattern components
125
(e.g., resist strips) of the other part at butting portion
136
, as is illustrated in FIG.
3
B. When each pattern component on one part is combined with the corresponding one on the other part, the resultant single pattern component has a size different from the designed one, inevitably deteriorating the precision of the resist pattern.
The problem with the butting portions of the pattern is prominent if an LSI pattern is formed by means of a mask-forming exposure apparatus (known as “photorepeater”). The mask-forming exposure apparatus projects a reduced image of a master mask on a mask layer. As shown in
FIG. 4
, the exposure apparatus comprises a projection optical system
142
. Shown in
FIG. 4
are a master mask
141
and a photomask
143
. The projection optical system
142
is a ⅕-reduction system that has a 22×22 mm field at the photomask dimension. The reduction ratio of the system is set to ¼ to form a pattern on a wafer. Therefore, two or more master masks must be jointed together and light must be applied to the wafer through the master masks in order to form chips having a size of 5.5×5.5 mm or more on the wafer.
A method of manufacturing an LSI pattern, in which master masks are jointed together to expose a wafer to light through them, will be explained with reference to the flow chart of FIG.
5
. This method differs from the method shown in the flow chart of
FIG. 1
in that a photorepeater is used to form a photomask. The chip-cutting tool used in this method performs the same function as the tool used in the process shown in FIG.
3
A. How the photomask is formed in this method will be described with reference to
FIGS. 6A
to
6
D. Assume that the data representing the layout of a product named “product”
11
is divided into four data items. Using the four data items, four master masks
151
to
154
are prepared. Light is applied to a photoresist layer, first through the first master mask
151
, then through the second master mask
152
, next through the third master mask
154
, and finally through the fourth master mask
154
. As a result, a photomask
155
is formed. In this case, the chip is divided into four parts, along the vertical center line and the horizontal center line. Therefore, cell B is divided into two parts B′ and B″, and cell D into two parts D′ and D″. Inevitably, the pattern in the cell B is cut into two parts, and the pattern in the cell D into two parts. Butting portions of the pattern are therefore formed on the wafer. As shown in
FIG. 6D
, resist strips
156
forming one part of the pattern may not align with resist strips
156
forming the other part of the pattern, at butting portion
157
, as is illustrated in FIG.
6
D. When each resist strip on one part is combined with the corresponding one on the other part, the resultant single resi
Higashikawa Iwao
Inoue Soichi
Kyoh Suigen
Mori Ichiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Rosasco S.
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