Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-06-01
2002-09-10
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S687000, C438S688000
Reexamination Certificate
active
06448185
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for making semiconductor devices.
BACKGROUND OF THE INVENTION
Dual damascene metal interconnects may enable reliable low cost production of integrated circuits using sub 0.18 micron process technology. To enable such interconnects to realize their full potential, the following method for making a semiconductor device has been proposed. In that method, a first etched region (e.g., a via or trench) is filled with a sacrificial light absorbing material (“SLAM”), after that region has been formed within a dielectric layer. That SLAM may comprise a dyed spin-on-glass (“SOG”) that has dry etch properties similar to those of the dielectric layer and light absorbing properties that enable the substrate to absorb light during lithography. After the first etched region is filled with the SLAM, a second etched region (e.g., a trench if the via is already formed or a via if the trench is already formed) is formed within the dielectric layer. Most of the SLAM may be removed as that second etched region is formed. Remaining portions of the SLAM are removed by a subsequent wet etch step.
The SLAM process reduces, or eliminates, substrate reflection and the need for high etch selectivity, ensuring that such effects will not adversely affect dual damascene via and trench formation. In addition to those issues, which the SLAM process addresses, decreasing device feature size reduces the distance between metal layers, which causes capacitance to increase. To address this problem, insulating materials that have a relatively low dielectric constant are being used in place of silicon dioxide to form the dielectric layer that separates the metal lines. Forming, for example, a low k dielectric layer from carbon doped oxide (“CDO”) instead of silicon dioxide to separate metal lines may yield a device having reduced propagation delay, cross-talk noise and power dissipation.
Although it is desirable to use CDO to form the dielectric layer for the above described SLAM process, current methods for removing photoresist and the SLAM from the device, after the trench is etched, can be relatively time consuming and expensive. To satisfactorily remove this material, it may be necessary to pass a device through a sequence of process steps, which include applying an oxygen plasma ash followed by a wet etch, more than once. Of even greater concern is that this current process for removing the photoresist and the SLAM may modify the etch profile in an undesirable manner. Another issue relates to how the conventional photoresist removal process may affect a CDO layer's dielectric properties. The carbon contained in such a layer may react with the oxygen based plasma used to remove the photoresist. That reaction depletes the amount of carbon contained in the layer, which raises the layer's dielectric constant.
Accordingly, there is a need for an improved process for making a semiconductor device that includes a dual damascene interconnect, which employs a sacrificial light absorbing material and a CDO containing dielectric layer to make such a device. There is a need for such a process that enables removal of photoresist and the SLAM from the device, after via and trench formation, without damaging the etch profile. There is also a need for such a process that requires less time and expense to apply. The method of the present invention provides such a process.
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Andideh Ebrahim
Myers Alan M.
Berry Renee R.
Ho Hoai
Seeley Mark V.
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