Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
1999-08-10
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
C257S354000
Reexamination Certificate
active
06372599
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (silicon-on-insulator) structure with a silicon layer formed on an insulator layer, and to a method of manufacturing it.
2. Description of Related Art
FIG. 8
shows a semiconductor device having a conventional SOI structure. As illustrated therein, an insulator layer
102
is formed on a semiconductor substrate
101
, and a silicon layer
103
is formed on the insulator layer
102
to give an SOI structure.
In the semiconductor element region comprising the silicon layer
103
, formed are source/drain regions
103
a
through doping with an impurity such as phosphorus, arsenic or the like, or boron or the like, and, in the area between the source/drain regions
103
a,
formed is a gate electrode
107
on the silicon layer
103
via a gate oxide film
106
therebetween to give a MOSFET.
A trench
104
is formed at the element-isolation area of the silicon layer
103
, and an insulating film
105
is formed within the inner wall of the trench
104
to give an element-isolation region, serving to isolate semiconductor elements from each other. As in
FIG. 8
, the bottom face of the silicon layer
103
makes an acute angle with the side of the element-isolation region (insulating film
105
) adjacent thereto.
An interlayer insulating film
108
is formed on the SOI substrate having the MOSFET thereon, and a conductive layer
109
is formed on the interlayer insulating film
108
. Contact holes for enabling electric connection between the conductive layer
109
and the source/drain regions
103
a
formed in the silicon layer
103
are formed through the interlayer insulating film
108
and filled with a conductor, via which the conductive layer
109
is electrically connected with the source/drain regions
103
a.
In the element-isolation region of the semiconductor device having the SOI structure of that type, the bottom face of the silicon layer
103
makes an acute angle with the side of the element-isolation region (insulating film
105
) adjacent thereto. In that condition, therefore, when the volume of the element-isolation region is varied through heat treatment to be effected after the formation of the element-isolation region, for example, through annealing to be effected after the formation of the oxide film
105
in the trench
104
, or through heat treatment to be effected in forming the gate oxide film
106
after the formation of the element-isolation region, the volume variation shall make the silicon layer
103
have large stress at the acute-angled corners of its bottom.
A technique for relaxing the large stress at the acute-angled corners of the bottom of the silicon layer
103
is disclosed, for example, in Unexamined Japanese Patent Publication No. (HEI)6-216230.
FIG. 9
shows an SOI structure for a semiconductor device illustrated in Unexamined Japanese Patent Publication No. (HEI)6-216230. As illustrated, the trench-shaped insulator of constructing an element-isolation region is so formed that its width in the cross section is continuously increased in the downward direction, in order that the bottom of the silicon layer does not make an angle with the element-isolation region adjacent thereto. Therefore, being different from that of
FIG. 8
, the semiconductor device of
FIG. 9
has no angle that may produce large stress, and the bottom of the silicon layer in
FIG. 9
is prevented from having any large stress. In
FIG. 9
, numeral references are the same as those in
FIG. 8
, provided that the element-isolation region
105
is formed of an isolating wall
105
b
in the trench
104
and a polysilicon layer
105
a
embedded therein.
In the semiconductor device noted above, however, the interface of the silicon layer adjacent to the insulator is formed to be convex toward the insulator. In this, therefore, when the stress resulting from the volume variation in the element-isolation region runs toward the silicon layer, it is concentrated in some parts in the silicon layer, as will be mentioned below. The problem caused by the stress concentration is that some lattice defects are formed in those parts with the stress concentrated.
The reason for the stress concentration is described with reference to FIG.
10
. As illustrated, in the semiconductor device of
FIG. 10
, the interface between the silicon layer and the insulator (trench) is so formed that, reaching the insulating layer, it is curved toward the silicon layer but not toward the element-isolation region. In this, therefore, when the stress resulting from the volume variation in the element-isolation region runs toward the silicon layer, as indicated by the arrows in
FIG. 10
, a plurality of stress components running in that direction shall be concentrated in the part as designated by “X” therein. As a result, some lattice defects are formed in that part of the silicon layer.
Meanwhile a semiconductor device having a trench-shaped insulator of which the width is continuously decreased in the downward direction, is disclosed in IEDM (International Electron Devices Meeting) Technical Digest, 1997, p.591. However, the semiconductor device disclosed has a large depression at the surface of the trench-shaped insulator near the semiconductor element region adjacent thereto. Thus, in the case where a gate electrode extends over the trench-shaped insulator as well as the semiconductor element region, a portion of the gate electrode will be embedded in the depression of the insulator so that the distance between the semiconductor element region and the portion of the gate electrode located on the insulator will be shortened in comparison with the case of no depression. With this structure, when a transistor controllable with such a gate electrode is formed in the semiconductor element region, it will likely be influenced by an electric field from the portion of the gate electrode embedded in the depression of the adjacent insulator, that is, an electric field will be concentrated in the semiconductor element region near the depression. As a result, a reverse narrow channel effect decreasing a threshold voltage occurs and a parasitic MOSFET tends to be generated in the semiconductor element region near the depression. The concentration of an electric field may also cause a deterioration of the semiconductor element region, such as silicidation of a contact portion of the source/drain region of the transistor.
On the other side, Unexamined Japanese Patent Publication No. (HEI)9-8118 discloses a process for forming a trench-shaped insulator without a depression at the surface near the semiconductor element region adjacent thereto, but the width of the trench-shaped insulator formed is constant in the downward direction.
SUMMARY OF THE INVENTION
The object of the invention is to provide a semiconductor device in which the stress from the volume variation in the element-isolation region to the silicon layer is relaxed to thereby protect the silicon layer from having lattice defects therein and in which the surface of the trench-shaped insulator in the element-isolation region does not have a depression near the semiconductor element region, and to provide a method of manufacturing it.
The semiconductor device of the invention comprises an SOI substrate with a silicon layer formed on an insulating layer, and a semiconductor element region and an element-isolation region formed in the silicon layer, wherein; the element-isolation region is of a trench-shaped insulator formed adjacent to the semiconductor element region, and the trench-shaped insulator is provided with a portion which is adjacent to the semiconductor element region, of which the width is continuously decreased in the downward direction, and of which the surface is planarized near the semiconductor element region. In the device, even when the volume variation in the element-isolation region produces some stress running toward the silicon layer, the stress to the silicon layer could be well relaxed. In addition, because the surface
Ipposhi Takashi
Iwamatsu Toshiaki
Miyamoto Shoichi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Vu David
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