Process of making buried capacitor for silicon-on-insulator...

Details Process of making buried capacitor for silicon-on-insulator... Process of making buried capacitor for silicon-on-insulator...

2000-11-07

2002-01-08

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Planar capacitor

C438S155000, C438S241000

Reexamination Certificate

active

06337253

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a capacitor for a silicon-on-insulator (SOI) structure and, more particularly, to a capacitor buried in an SOI structure and to a process for fabrication.
BACKGROUND OF THE INVENTION
High-performance circuits require high-value, low-impedance decoupling capacitors between the DC power supply and ground lines to limit noise created by the rapid switching of current. This noise can arise, for example, due to inductive and capacitive parasitics. Ideally, decoupling capacitors are placed as close as possible to the load in order to enhance their effectiveness in reducing the noise in power and ground lines. Consequently, decoupling capacitors have been fabricated directly on the chip.
Unfortunately, the resistance of inversion capacitors for SOI (silicon-on-insulator) or bulk MOS (metal oxide semiconductor) high-performance circuits is excessively high for decoupling of high frequency noise because of the inversion layer resistance. Inversion layer resistance is representative of coupling impedance. Accumulation capacitors have proven to be effective in bulk MOS structures, but they are not a viable option for SOI structures because of the high resistance of the thin silicon layer on the insulator.
Furthermore, due to other device considerations, thinner SOI layers are constantly being sought. Thin SOI layers aggravate the decoupling problem. Unfortunately, none of the decoupling capacitor approaches commonly practiced for bulk MOS technologies provide a fully acceptable solution for high-performance SOI circuits.
An additional problem with SOI structures is caused by the poor thermal conductivity of the buried oxide layer: SOI devices that dissipate relatively high power levels are thrown out of electro-thermal equilibrium with their environment. Furthermore, SOI devices experience higher operating temperatures than their bulk device counterparts. One process of alleviating the high operating temperature problem is to increase the area of the gate layer over an inversion-type decoupling capacitor. Unfortunately, this approach suffers from the drawback that the approach increases the amount of silicon real estate required to constitute the fabricated circuit. Moreover, the SOI capacitors still have higher-than-desired impedance. Thus, the high inversion layer resistance described above is not easily solved in conventional SOI technology even by increasing the area of the capacitor.
The deficiencies of the conventional use of decoupling capacitors show that there is a need for a decoupling capacitor that effectively reduces noise in power and ground lines while minimally occupying valuable silicon real estate. To overcome the shortcomings of the conventional processes, a new process is provided. An object of the present invention is to provide a decoupling capacitor of very low impedance for high-performance circuits, such as those fabricated with SOI and MOS technology. A related object is to provide a low-impedance decoupling capacitor that preserves valuable silicon real estate while also reducing noise in the power and ground lines.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a buried decoupling capacitor (hereinafter “buried capacitor”) in the body of a p-type silicon base layer in the space under an active semiconductor device. This structure results in a buried capacitor in an SOI structure. The buried capacitor is a p-n
+
junction. The process of the invention comprises the steps of:
forming a buried oxide layer and a silicon layer in a p-type silicon base layer;
forming an n
+
layer extending parallel to the buried oxide layer in a portion of the p-type silicon base layer; and
forming electrically conductive paths to the p-type silicon base layer and the n
+
layer extending through the buried oxide and silicon layers.
The n
+
layer can be formed ether adjacent the p-type silicon base layer surface or below the p-type silicon base layer surface. In addition, the n
+
layer can be formed either as a uniform layer or as a plurality of discreet n
+
layers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


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