DRAM circuit and its sub-word line driver

Details DRAM circuit and its sub-word line driver DRAM circuit and its sub-word line driver

2001-02-14

2002-07-16

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110

Reexamination Certificate

active

06421295

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a dynamic random access memory (DRAM) circuit. More particularly, the present invention relates to a DRAM circuit and its associated sub-word line driver.
2. Description of Related Art
In general, the word lines in a memory unit are designed using a variety of methods. However, some design considerations are fundamental. For example, maintaining a constant potential on the word line so that the memory unit can operate reliably, and limiting propagation delay of signals to memory cells are major considerations. Conventionally, a boost circuit is often added to DRAM to improve performance.
To employ a boost circuit in a DRAM unit, a control signal must be used to monitor the voltage level generated by the boost circuit. The most commonly used signal is a row access strobe (RAS) signal. Typically, when the RAS signal is at a high potential level, the boost circuit will drive the output potential to a voltage needed for operation. On the other hand, when the RAS signal is at a low potential level, the boost circuit will drive the output potential to a level identical to an internal supply voltage. Because this type of architecture uses a single word line, propagation delay for boosting voltage presents little problem when memory capacity is small (such as a
64
MB memory unit). However, memory capacity of recent memory units has expanded so much that this type of single-word-line memory circuit may have too large of propagation delay to the memory cells. In other words, the resistance-capacitor (RC) delay is too long and may lead to a lowering of memory operating speed.
To resolve the RC delay time problem, a hierarchical DRAM circuit is developed.
FIG. 1
is a block diagram showing a conventional hierarchical DRAM circuit. As shown in
FIG. 1
, the booster circuit includes a voltage regulator
102
, a charge pump
100
and a charge reservoir
104
. Boost voltage from the booster circuit is output to a reverse-phase network
108
. In addition, the voltage level of the boost voltage is maintained at a constant operation voltage by sensing any difference between the current boost voltage and the desired voltage level through the voltage regulator
102
, and boosting the level using the charge pump
100
and holding charges in the charge reservoir
104
. Thereafter, the address stored in an address buffer
110
is sent to decoders
112
and
114
. The decoded results determine whether a main word line (MWL) driver
118
drives the main word line or a main word line driver
120
drives the main word line. Furthermore, the least significant bit in the address is decoded by a decoder
116
to determine the output from a reverse-phase network
108
via a selection signal SELN. Hence, one of the sub-word line (SWL) drivers (such as sub-word line drivers
122
,
124
,
126
etc.) is selected. With this arrangement, the boost voltage can be rapidly transferred from the reverse-phase network
108
via signal line BST to a target memory cell for reading (such as memory cell
130
) according to the selected main word line and signal SELN selected sub-word line.
Due to various combinations between main word lines and sub-word lines, the path needed for a boost voltage to propagate to a particular memory cell is shortened. Hence, operating time is also shortened. However, to be able to supply the desired output operating voltage at any time, the voltage level of the boost voltage must be maintained at the operating voltage level. Consequently, this type of design is bound to waste a lot of energy unnecessarily.
In summary, defects in a conventional DRAM circuit and its associated sub-word line driver design include:
1. Single word line architecture is acceptable only for memory having a small memorizing capacity because the operating delay will be too large for a large capacity memory.
2. In hierarchical circuit design, the voltage level of the boosting voltage must be maintained at a high operating voltage, thereby wasting a lot of energy.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a dynamic random access memory (DRAM) circuit having a boost circuit, a main word line driver and a sub-word line driver. The boost circuit changes its output boost voltage, which lies between an internal supply voltage and an operating voltage, according to an input row access strobe (RAS) signal. The main word line driver is connected to the output terminal of the boost circuit. The main word line is selected according to the input address decoding driven by the boost voltage. The sub-word line driver is connected to the main word line. An even or odd sub-word-line signal is generated according to the least significant bit of an input address so that the voltage level of the main word line can be used to drive the corresponding sub-word line.
This invention also provides a sub-word line driver for DRAM. The sub-word line driver includes a first and second relay transistor, a first and second pull-down transistor, and a first and second pass transistor. The source/drain terminals of the first relay transistor are connected to a main word line and an even sub-word line. The gate terminal of the first relay transistor is connected to an odd sub-word line. The source/drain terminals of the second relay transistor are connected to the main word line and the odd sub-word line. The gate terminal of the second relay transistor is connected to the even sub-word line. The source/drain terminals of the first pull-down transistor are connected to the even sub-word line and a reference voltage point. The gate terminal of the first pull-down transistor is connected to a terminal for receiving an even sub-word-line signal. The source/drain terminals of the second pull-down transistor are connected to the odd sub-word line and the reference voltage point. The gate terminal of the second pull-down transistor is connected to a terminal for receiving an odd sub-word-line signal. The source/drain terminals of the first pass transistor are connected to the main word line and the even sub-word line. The gate terminal of the first pass transistor is connected to the terminal for receiving the odd sub-word-line signal. The source/drain terminals of the second pass transistor are connected to the main word line and the odd sub-word line. The gate terminal of the second pass transistor is connected to the terminal for receiving the even sub-word-line signal.
In brief, this invention employs a hierarchical DRAM circuit and a system for automatically changing the voltage level of a boost voltage. Besides the capacity for a faster response from the circuit, considerable power is saved as well. In addition, the sub-word line driver in this invention is capable of controlling a pair of sub-word lines, thereby reducing the length of the main word line considerably. Since the path and propagation time of the boost voltage is shortened compared with a conventional hierarchical DRAM circuit, the operating speed of the memory is greatly increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5184035 (1993-02-01), Sugibayashi
patent: 5946243 (1999-08-01), Sim
patent: 6011246 (2000-01-01), Oh
patent: 6144589 (2000-11-01), Michelson et al.
patent: 6160753 (2000-12-01), Shibatama
patent: 6278640 (2001-08-01), Lines

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