Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1998-12-14
2002-01-01
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S002000, C703S005000, C382S141000, C382S145000, C382S149000, C706S052000
Reexamination Certificate
active
06336086
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods and systems for analyzing and troubleshooting a fabrication process.
DESCRIPTION OF THE RELATED ART
In semiconductor fabrication, wafers from the same lot do not always have the same yield. Although the yield lost in every wafer may originate during any step of the fabrication routing, very often most of the lost yield can be attributed to just one step, and affects some or all the wafers within the lot. In this particular “killing” step, wafers may have been processed sequentially one-by-one, in a multi-chamber tool, or the whole lot simultaneously. However, when one of the chambers of a multichamber tool impacts the yield, only the wafers which pass through that chamber are affected. If the processing order (by bar-code reading the wafers) for that tool is recorded, there is a relation between wafer number and yield. In the same way yield loss may be related to other type of process tools.
The inventors previously developed an advanced software system, (POSITRAK) to correlate processing order and yield. This system is described in M. Recio, A. Fernández, V. Martin, M. J. Pemán, G. González, J. R. Hoyer, S. Whitlock, D. James and M. Hansen. “Advanced Software System for Yield Improvement in Manufacturing Fab”. Proceedings on SPIE's 1996 Microelectronic Manufacturing, vol.2874, pp.219-229, 1996, which is incorporated by reference herein in its entirety.
Yield losses produced in different process tools may exhibit a type of footprint that is referred to herein as an “order pattern”. POSITRAK correlates a yield metric (at the wafer level) with the process order of the wafers within the lot during a set of fabrication steps The main output it provides is the lot-step order plot, such as those in the second column of FIG.
1
.
FIG. 1
is a table showing five different order patterns observed in fabrication processes in various types of machines. The first column of
FIG. 1
is a name given to each of these order patterns. The second column contains an X-Y plot for each type of order pattern, in which the horizontal axis (independent variable) is the positioning or order of the wafers withing a lot at the particular step in the fabrication line in which the order pattern is observed; the vertical axis (dependent variable) is a quantitative measure of the yield. Thus, the dots at the top of each plot indicate high yield wafers, and the dots at the bottom of each plot indicate low yield wafers. The third column indicates the type of process in which the order pattern is observed. The fourth column indicates the problem which gives rise to the low yield observed in the wafers represented by the dots at the bottom of each plot.
For example, in the first row, an order pattern referred to as a “⅓” pattern, every third wafer which passes through a particular machine is observed to have a low yield metric. This type of order pattern is most likely to occur in a three chamber machine. When one of the chambers of a three-chamber tool is impacting yield, only the wafers passing through that chamber are affected.
In the second row, a “½” pattern is described. This type of order pattern is most likely to occur in a to chamber machine. When one of the chambers of a two chamber tool is impacting yield, only the wafers passing through that chamber are affected.
In the third row, there is no gradual trend. Wafers with low yield are grouped together in one or more batches. This occurs in batch type processes.
In the fourth row, degrading yields are observed. This indicates bad conditions between wafers. Similarly, in the fifth row, where low yields are only observed in the first few wafers, a poor initial condition is indicated.
There several common lot-step plots that are referred to as “order patterns” that have been repeatedly observed.
As mentioned above, wafer order is read at each module of the routing and wafers are randomized, or rearranged in a random order. That is, the order in which the wafers are processed in one step (or set of steps) differs from the order in which the wafers are processed in any other step (or set of steps). At each step, the wafer order is identified (for example, with a bar code scanner). In this way, when an order pattern shows up at a certain module (set of process steps), it does not show up at any other module of the fabrication routing, due to the randomization executed. Therefore, if there is any type of order pattern at any of the modules, POSITRAK can pinpoint it as origin of the yield loss. Moreover, if the order pattern can be linked (as shown on
FIG. 1
) to a specific type of machine, the analyst can identify the one process causing the yield loss.
One of the great advantages of POSITRAK is its ability to work with many different metrics associated with low yield. Yield results (taken as pure yield of separate test bins) E-test results, particle counts, in-line parametric data (e.g., polysilicon line width),.and the like may be used by POSITRAK to trace the sources of problems. Creating (and adjusting) an algorithm for each source of data would be completely undesirable. But, at the same time, the above-mentioned metrics have different ranges of variation (i.e. particles many vary form a few to hundreds, while yield variations are very much smaller). This makes it difficult to find an algorithm able to work with all sources of data.
Also, although the graphical plots shown in
FIG. 1
may be studied by an analyst, and the analyst may use his knowledge and experience to identify the problem which is impacting the yield. However, this analysis by a human is time consuming. When a large number of lots must be analyzed, an automated tool is desired.
SUMMARY OF THE INVENTION
The present invention is a method and system for analyzing a process (having a plurality of processing steps) for forming a plurality of objects, wherein three different algorithms are used to identify order patterns; and one of the order patterns is selected.
A plurality of data representing characteristics of each object are extracted. A first order pattern is identified in any one of the processing steps using a decision tree, based on the data representing characteristics. A second order pattern is identified in any one of the processing steps by comparing the data representing characteristics to a predetermined threshold. A third order pattern is identified in any one of the processing steps based on a calculated distance from a centroid computed from the data representing characteristics. One of the first, second, and third order patterns is selected, and one of the processing steps is identified as being associated with the selected order pattern.
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Alonso Miguel Angel Merino
Garrido Julian Moreno
Maria Victorino Martin Santa
Perez Almudena Fernandez
Segoviano Miguel Recio
Agere Systems Guardian Corp.
Koffs Steven E.
Morris &
Phan Thai
Teska Kevin J.
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