Split-gate flash memory cell with separated and self-aligned tun

Details Split-gate flash memory cell with separated and self-aligned tun Split-gate flash memory cell with separated and self-aligned tun

1994-07-01

1995-06-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 52, 437 48, 148DIG109, H01L 218246

Patent

active

054279682

ABSTRACT:
An electronically erasable and reprogrammable memory integrated circuit device having split-gate memory cell with separated tunneling regions and its process of fabrication are disclosed. A silicon substrate having field oxide layers isolating component regions are processed to construct a memory cell in each of the isolated component region. Each of the memory cells includes a drain and source region formed in the silicon substrate, with a channel formed between the drain and source regions. Ring-shaped floating gate surrounds and covers the periphery of the channel and is isolated with the drain and source regions respectively by two thin tunneling oxide layers that are separated from each other. The two separated tunneling oxide layers constitute two separated tunneling regions. A control gate layer covers the ring-shaped floating gate and the portion of the channel that is not covered by the floating gate layer, and is separated from the floating gate by an isolation layer. A gate oxide layer is formed between the control gate layer and channel.

REFERENCES:
patent: 5019879 (1991-05-01), Chiu
patent: 5268319 (1993-12-01), Harari
patent: 5268585 (1993-12-01), Yamauchi
patent: 5284784 (1994-02-01), Manley

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