Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-03-09
2002-05-14
Smith, Matthew (Department: 2825)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S319000
Reexamination Certificate
active
06388498
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, more specifically to a semiconductor device having a digital circuit and an analog circuit in one chip.
2. Description of the Background Art
Due to an advancement in the technical field of semiconductor devices, it is becoming a common practice to integrate two types of circuits, respectively processing analog and digital signals, in one chip. Therefore, well regions for digital and analog circuits are separated to be externally supplied with power from different power supplies to avoid interference by noise.
FIG. 10
is as schematic block diagram showing a structure of a conventional semiconductor device
501
having an analog circuit and a digital circuit.
Referring to
FIG. 10
, semiconductor device
501
includes an analog circuit portion
502
externally receiving an analog input signal for process, and a digital circuit portion
504
receiving data from the analog circuit portion for a prescribed operation and feeding back the operation result to the analog circuit portion.
Analog circuit portion
502
includes a sample circuit
508
receiving and sample-holding an analog input signal AIN and performing a sample-and-hold operation thereon, a DA converter
510
converting a digital signal from the digital circuit portion to an analog signal, a comparator
512
comparing outputs from sample circuit
508
and DA converter
510
, and a latch circuit
528
latching an output from comparator
512
.
Digital circuit portion
504
includes a result register
516
receiving and storing an output from latch circuit
528
, a CPU (Central Processing Unit)
514
outputting an instruction signal for a control in accordance with a content of the result register, a control register
518
holding the instruction signal output from CPU
514
, and a control circuit
520
for a process in accordance with a content of control register
518
.
Control circuit
520
outputs a control signal to DA converter
510
included in analog circuit portion
502
. Control circuit
520
includes a buffer circuit
526
outputting the control signal at its outputting portion.
An analog power supply potential AVDD and an analog ground potential AVSS are externally applied to analog circuit portion
502
. A digital power supply potential DVDD and a digital ground potential DVSS are applied to digital circuit portion
504
. Namely, the power supply potentials are externally applied to the analog and digital circuit portions separately.
FIG. 11
is a circuit diagram shown in conjunction with a connecting portion between an output stage of buffer circuit
526
and an input stage of DA converter
510
in FIG.
10
.
Referring to
FIG. 11
, an output portion of buffer circuit
526
in
FIG. 10
includes an inverter
552
. An input portion of DA converter
510
includes an inverter
556
.
Inverter
552
includes a P channel MOS transistor
558
and an N channel MOS transistor
560
having their gates connected to an input node N
11
and connected in series between a node supplied with digital power supply potential DVDD and a node supplied with digital ground potential DVSS. A connection node between P channel MOS transistor
558
and N channel MOS transistor
560
is a node N
12
.
Inverter
556
includes a P channel MOS transistor
566
and an N channel MOS transistor
568
having their gates connected to node N
12
and connected in series between a node supplied with analog power supply potential AVDD and a node supplied with analog ground potential AVSS. A connection node between P channel MOS transistor
566
and N channel MOS transistor
568
is a node N
13
.
FIG. 12
is a cross sectional view showing a structure of a semiconductor substrate at the connecting portion shown in FIG.
11
.
Referring to
FIGS. 11 and 12
, inverters
552
and
556
are respectively formed in digital and analog circuit regions. In the digital circuit region, N and P wells
572
and
576
are formed in a main surface of a substrate
500
. P channel MOS transistor
558
and an N type impurity region
574
are formed in N well
572
. N type impurity region
574
and a source of P channel MOS transistor
558
are both connected to digital power supply potential DVDD.
N channel MOS transistor
560
and a P type impurity region
578
are formed in P well
576
. A source of N channel MOS transistor
560
and P type impurity region
578
are both connected to digital ground potential DVSS.
In the analog circuit region, N and P wells
592
and
596
are formed in the main surface of substrate
500
. P channel MOS transistor
566
and an N type impurity region
594
are formed in N well
592
. A source of P channel MOS transistor
566
and N type impurity region
594
are both connected to analog power supply potential AVDD.
N channel MOS transistor
568
and a P type impurity region
598
are formed in P well
596
. A source of N channel MOS transistor
568
and P type impurity region
598
are both connected to analog ground potential AVSS.
As is apparent from the cross sectional structure, in the conventional semiconductor device, wells respectively formed for the elements of digital and analog circuits are separated and supplied with different power supply potentials. Thus, interference by noise is not caused by the circuits.
However, as the interface portion for transmitting a signal and from the digital and analog circuits is arranged in one of the wells of analog and digital circuit regions, the noise may disadvantageously be propagated through the interface circuit.
FIG. 13
is a schematic diagram showing waveforms in conjunction with propagation of noise.
Referring to
FIGS. 12 and 13
, when a potential of node N
11
falls from an H to L level, P channel MOS transistor
558
is rendered conductive and N channel MOS transistor
560
is brought into a non-conductive state. Responsively, node N
12
rises from the L to H level. At the time, power supply noise is caused to digital power supply potential DVDD due to noise caused by switching the MOS transistor or the like.
Then, noise is also superimposed on the signal output from the circuit which is supplied with digital power supply potential DVDD as a power supply potential. Therefore, the waveform at node N
12
is also affected by the noise. The waveform affected by the noise controls conductivities of P and N channel MOS transistors
566
and
568
. As a result, analog power supply potential AVDD is also affected by the noise caused to the digital power supply potential.
Noise is most likely to be generated around the output buffer and clock to an external portion in the digital portion. The generated noise is propagated to the analog portion while being superimposed on the power supply and the signal line. For example, an AD converter converting an analog signal of 5 volts to a digital signal of 10 bits is affected considerably by noise as it operates at a resolution of 5 volts divided by 1024, that is, at 5 mV.
Noise from the analog portion to the digital portion is the noise that has been superimposed on an analog signal input or generated during operation of an operational amplifier in the analog portion. Recently, while not as low as an operating power supply voltage of the analog circuit, the operating power supply voltage of the digital circuit is becoming lower and the operation is considerably affected by noise.
Thus, unless interference of analog and digital circuits by noise is reduced, a desired high performance is not obtained and malfunction is caused.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device preventing interference of analog and digital circuits and reducing a level of noise.
In short, the present invention is a semiconductor device including a single semiconductor chip. The semiconductor device is provided with first, second and third high potential power supply terminals, first, second and third low potential power supply terminals, first and second internal circuits, and an interface circuit.
The firs
Azekawa Yoshifumi
Chiba Osamu
Moriwaki Shohei
Shimakawa Kazuhiro
Dinh Paul
Smith Matthew
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