pMos analog EEPROM cell

Details pMos analog EEPROM cell pMos analog EEPROM cell

2000-10-27

2002-09-17

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185280, C257S314000, C257S315000

Reexamination Certificate

active

06452835

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to an analog memory cell. More particularly, the present invention is directed to an analog EEPROM (electrically erasable programmable read only memory) device for use in storage and retrieval of analog signals on a floating gate. Still more particularly the present invention is directed to a pMOS analog EEPROM cell using Impact Ionization to generate hot electrons for injection from the drain-channel depletion region to the floating gate and Fowler-Nordheim tunneling to remove electrons from the floating gate.
2. The Background Art
A primary goal of the research leading to the present invention is the development of silicon learning systems and analog memory-storage systems. One impediment to achieving these goals has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Prior efforts typically used capacitive storage with clocked refresh as described in B. Hochet, et al.,
“Implementation of a Learning Kohonen Neuron Based on a New Multilevel Storage Technique,” IEEE J. Solid
-
State Circuits,
vol. 26, no. 3, pp. 262-267, 1991, or storage of a multi-bit digital equivalent word as described in P. Hollis and J. Paulos, “
A Neural Network Learning Algorithm Tailored for VLSI Implementation,” IEEE Trans. Neural Networks,
vol. 5, no. 5, pp. 784-791, 1994. Such approaches result in large and complex devices which are usually power hungry. Nonvolatile floating-gate devices, such as EEPROM transistors, typically are optimized for binary-valued data storage rather than analog use (see, e.g., F. Masuoka, R. Shirota, and K. Saku,
“Reviews and prospects of non-volatile semiconductor memories,” IEICE Trans.,
vol. E 74, no. 4, pp. 868-874, 1991), and do not compute their own memory updates.
Unlike conventional EEPROM transistors, the guarded-pFET synapse described herein allow simultaneous memory reading and writing. Consequently, it is possible to apply continuous negative feedback during the write process to store an analog memory value in a single-step write. This process is called self-convergent writing: an intrinsic, self-limiting feedback path within the transistor itself ensures that the analog memory value is stored accurately.
To achieve a substantial improvement over current technology silicon learning systems, a single transistor learning device with the following attributes would be very valuable:
1. Non-volatile analog storage;
2. Bi-directional memory writing;
3. Support for simultaneous memory reading and writing;
4. On-chip read/write driver circuitry operating off of a single polarity voltage supply;
5. Self-convergent memory writing;
6. Low power consumption;
7. Compact size; and
8. Compatibility with standard silicon MOS processing.
Prior art floating gate transistors, which use electrical charge stored on a floating polysilicon gate embedded in an insulator such as silicon dioxide, provide suitable nonvolatile analog storage. The charge on such a floating gate is known to remain fixed for periods of many years. Although the advantages of using floating gate transistors as memory elements are well known, J. Lazzaro, et al., “Systems Technologies for Silicon Auditory Models,” IEEE Micro, Vol. 14, no. 3, pp. 7-15, 1994, T. Allen, et al., “Writable Analog Reference Voltage Storage Device,” U.S. Pat. No. 5,166,562, 1991, their application to silicon learning networks and analog memory cells has been limited. The principal reason has been the lack of suitable bi-directional and self-convergent mechanisms for writing the analog memory. Since the gate of a floating gate transistor is completely embedded within an insulator, writing the memory involves moving charge carriers through this insulator. Many mechanisms are known which will move electrons through an insulator. Two of the most common and most easily controlled methods are tunneling and hot-electron injection. The inherent difficulty in performing these operations has been the primary impediment to implementation of floating gate transistors in silicon learning and analog memory systems.
The difficulty in transporting electrons across the barrier presented by the silicon/oxide interface is depicted in FIG.
1
. Surmounting the barrier
10
requires that an electron possess more than about 3.2 eV of energy. At room temperature the probability that semiconductor electrons will possess this energy is exceedingly small. Alternatively, an electron could tunnel through this barrier; however, at the voltages and oxide thicknesses used in conventional silicon MOS processing, the tunneling probability is also exceedingly small.
Fowler-Nordheim (FN) tunneling involves applying a voltage across the oxide
12
, as shown in
FIG. 2
which enhances the probability of an electron tunneling through it. Tunneling current versus oxide voltage for a 400 Å SiO
2
gate oxide typical of a 2 &mgr;m MOS process is shown in FIG.
3
. Bi-directional currents through the oxide are required to achieve the learning and unlearning functions necessary in a silicon learning cell, and the writing and erasing necessary in an analog memory cell. Although the tunneling process has no preferred direction, bi-directional tunneling requires either dual polarity high voltages, or a single polarity high voltage and a means for pulling the floating gate to this voltage when adding electrons, and pulling it near ground when removing them. Both approaches are unattractive. The dual polarity solution requires a negative voltage much lower than the substrate potential; the single polarity solution does not support simultaneous memory reading and writing or self-convergent memory writes.
Single polarity bi-directional tunneling is often used in writing digital EEPROMs. Since writing the memory involves pulling the floating gate either to the supply voltage or to ground, the EEPROM cell cannot be read during the write process. Excess charge is typically added to the floating gate to compensate for this lack of memory state feedback. Although excess charge is acceptable when writing a binary valued “digital” memory, where the exact quantity of charge is irrelevant once it exceeds the amount necessary to completely switch the device to one of its two binary states, uncertainty in the amount of charge applied to an analog memory cell results in significant memory error. Because the memory-write process is not self-convergent, analog EEPROMS use inerative writes. This need has not been satisfied adequately by commercial nFET EEPROMs, primarily because conventional EEPROM transistors do not permit simultaneous memory reading and writing. Most analog EEPROM implementations require iterative writes: the memory first is written, then is read; the written and read values then are compared, and the error is used to write a correction. This cycle is repeated until the error is within prescribed bounds.
Hot-electron injection is a process whereby electrons near the surface of a semiconductor acquire more than about 3.2 eV of energy, typically by acceleration in an electric field, and then surmount the silicon/oxide barrier. Once in the silicon dioxide conduction band, an electric field applied across the oxide carries these electrons to the floating gate. There are a number of ways of accomplishing hot-electron injection.
One source for a high electric field is the collector-to-base depletion region of either a vertical or lateral bipolar junction transistor (BJT). An example of a lateral BJT used in a similar application is shown in U.S. Pat. No. 4,953,928 to Anderson, et al. Although this device is suitable for analog learning applications, each learning cell requires both an injection BJT and a MOSFET, the former to effect hot-electron injection and the latter to read the stored charge. A reduction in the number of transistors per cell would be highly desirable.
Another source for a high electric field is in the channel region of a split-gate n-type MOSFET. Split-gate injectors, as shown and described in U.S

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