Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
1999-01-22
2002-01-29
Pham, Chi (Department: 2631)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S136000, C375S140000, C375S343000, C370S335000, C708S300000, C708S319000
Reexamination Certificate
active
06343094
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to Code Division Multiple Access (CDMA) signal reception in cellular communication, and more specifically to a simplified matched filtering method and system, which requires less energy than known systems.
BACKGROUND OF THE INVENTION
In general, Code Division Multiple Access (CDMA) receivers, as shown in
FIG. 1
, generally at
10
, as used for cellular communication, include a radio frequency (RF) front end
12
, an analog-to-digital (A/D) converter
14
, and a base-band signal processor
16
. Base-band signal processor
16
further includes matched filters
18
,
20
, which provide filtered output signals to a control processor
26
, which in turn provides a signal
28
to a RAKE receiver
30
. Control processor
26
also generates a number of control signals, which will be described later herein. Such CDMA receivers are, of course, battery powered, generally by rechargeable batteries. Providing a CDMA receiver that uses a minimal amount of power, and therefore has an extended battery life between charges is desirable.
In one type of prior art system, an input signal
32
is amplified, down-converted from RF frequency to IF, or base-band frequency, and then split into an in-phase signal (I) and quadrature-phase signal (Q) in RF front end
12
, as shown in
FIG. 1. I
signal
36
is an input to A/D converter
14
a
while Q signal
38
is an input to A/D converter
14
b.
The split signals are converted from analog to digital signal by A/D converter
14
so that multiple bits represent the base band signal strength and the polarity. Digital I signal
36
D and digital Q signal
38
D are the input of matched filters
18
,
20
, respectively, and also RAKE receiver
30
in base-band signal processor
16
.
Each matched filter, such as filter
18
, shown in
FIG. 2
, includes a multiplier portion, shown generally at
40
, an adder portion
42
, and a shift register
44
. Shift register
44
includes a number of delay elements,
46
-
54
. The number of delay elements in the matched filters is determined by the sample rate, i.e. multiplication of the number of chips per symbol and the number of samples per chips. Each output of the delay element is the input of consecutive delay element, and also it is multiplied by the coefficient, C
0
-C
N
, determined by the spreading sequence provided from the outside of the matched filter and summed for computing the correlation of the predetermined sequence.
The other prior art system is Exclusive-OR operation to the shift register output and the coefficient. The output of the adder is the output of the matched filter, and the I and Q matched filter outputs are applied to determine the receiving path characteristics, such as signal strength, phase, and delay in the control processor. The control processor assigns the delay amount to each finger of the RAKE receiver to demodulate the path, based on the information from matched filter output. RAKE receiver performs despreading and coherent detection, and outputs the received data stream, and the data stream is processed to obtain the needed data. The “power and clock source” supplies the needed power and clock to all blocks. In both types of systems, the matched filters require considerable power, and tend, therefor, to decrease battery life.
However, known systems do not describe a method or structure to reduce the current consumption in the matched filter. Particularly, the prior art does not teach or suggest how to reduce the current consumption in the matched filter when the matched filter output is applied to compute the signal-to-noise ratio and the amount of delay for the RAKE fingers.
U.S. Pat. No. 5,293,398, to Hamoa et al., granted Mar. 8, 1994, for “Digital Matched Filter,” describes a filter system where different bits of a received signal are converted into a multi-bit signal and are input into different correlators in a digital matched filter, which is used as a correlator in a receiver in an spread spectrum communications (SSC) system. After having weighted correlation outputs, the different weighted correlation outputs are added together and weighting factors are varied, depending on a synthesized correlation output obtained by addition. In this system the correlators are constructed similarly to one another and are driven by the same clock rate as the remainder of the system.
U.S. Pat. No. 5,623,485, to Bi, granted Apr. 22, 1997, for “Dual Mode Code Division Multiple Access Communication System and Method,” describes a CDMA communication system capable of operating at higher data rate with fewer bit errors and reduced co-channel interference, which facilitates coherent detection without the use of a pilot signal. The system includes a transmitter and a receiver. The communication system may be used as a forward and/or received communications link in a cellular telephone system. The CDMA signal receiver includes matched filters which detects the signal spread by PN sequence and Walsh sequence, and the matched filter output is applied to computing the channel estimates for coherent decoding.
U.S. Pat. No. 5,659,574, to Durrant et al. granted Aug. 19, 1997 for “Multi-Bit Correlation of Continuous Phase Modulated Signal,” describes a technique for demodulating continuous phase modulation (CPM) spread spectrum signals and variations. A plurality of A/D converters in a receiver quantitize the demodulated signals into multi-bit digital signals prior to correlation. Multi-bit correlators operate on the multi-bit digital signals to produce correlation signals that are combined to form a unified correlation signal for detection. A receiver splits into two signals and correlates a plurality of chip sequence (e.g., I and Q), ultimately combining the result into a unified correlation.
Nakamura et al.,
Configuration and characteristics Estimation of a W
-
CDMA systems for Third Generation Mobile Communications,
Proc. IEEE Vehicular Technology Conference (VTC'98), pp973-977, May, 1998, describes a wide-band CDMA system to evaluate the performance of a total mobile communications system.
Matsuyama et al.,
A Performance of W
-
CDMA demodulator with matched filter,
(Japanese), IEICE conference '97, B-5-11, Apr. 1997, describes performance characteristics of a wide-band CDMA demodulator.
S. Seo et al.,
SIR measurement scheme using pilot symbols for transmit power control of DS
-
CDMA
(Japanese), Technical Report of IEICE RCS96 -74, Aug. 1996, describes a DS-CDMA system which is responsive to traffic levels and distance to station.
SUMMARY OF THE INVENTION
An improved filter for use in a CDMA receiver having an RF front end for splitting a received signal into I and Q components, A/D converters for converting the I and Q components into I and Q digital components, a control processor for controlling the receiver, a system clock and a power supply, the improved filter including a matched filtering mechanism, wherein each filter includes: a separation mechanism to separate a digital I signal and a digital Q signal into MSB and LSB signal components; a MSB sub-portion having multiple MSB delay elements, a multiplier associated with each delay element, and a MSB adder for processing said MSB signal components; a LSB sub-portion having multiple LSB delay elements, a multiplier associated with each delay element, and a LSB adder for processing said LSB signal components, wherein said LSB sub-portion has fewer delay elements than said MSB sub-portion; a third adder for adding said processed MSB and LSB signal components to provide a filter output; and a half clock generator for supplying a half-clock signal to said LSB portion. A method of filtering a digital signal in a CDMA receiver includes dividing a digitized signal into MSB and LSB components; processing the MSB components with a first predetermined number of delay and multiplication operatives; and processing the LSB components with a second predetermined number of delay and multiplication operative, wherein the second predetermined number is less than the first predetermined number.
An
Nguyen Dung X.
Pham Chi
Sharp Laboratories of America Inc.
Varitz PC Robert D.
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