Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-03-20
2002-05-14
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000
Reexamination Certificate
active
06388945
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to a semiconductor memory device for inputting and outputting data in synchronization with an external clock signal.
2. Description of the Related Art
Recently, a Dynamic Random Access Memory (DRAM) has been facing requirements, such as to operate at high speed, to consume less electric power, and to have a high-speed interface. In this trend, a Synchronized DRAM (SDRAM) is a mainstream type of the DRAM, the SDRAM inputting and outputting data in synchronization with a clock signal. Even a DDR (Double Data Rate) type is proposed to enhance an interface speed This DDR type outputs data by using a clock signal CK and a reverse clock signal /CK so as to increase an output rate. In any type of the DRAM, an operating frequency has to be increased so as to achieve a high-speed interface.
However, when a high-frequency clock signal controls an internal operation, a margin in a specification becomes smaller as the frequency of the clock signal becomes higher, making it difficult to guarantee a reliability of the internal operation. Therefore, an operating frequency of the internal operation has to be decreased by such method as a frequency dividing.
The above-mentioned decrease in an operating frequency is especially employed in controlling a data output. Hereinafter, a description will be given, with reference to the drawings, of a conventional semiconductor memory device having this function.
FIG. 1
is an illustration of a structure of a conventional semiconductor memory device. As shown in
FIG. 1
, the conventional semiconductor memory device comprises: pads
1
,
3
,
5
and
33
; clock buffers
7
and
8
; a command buffer
9
; a frequency divider
11
; a command recognition unit
13
; a DLL (Delayed Locked Loop) circuit
15
; an output signal generating circuit
17
; a 0° logic circuit
19
; a 180° logic circuit
21
; an output control unit
23
; a readout circuit
25
; a memory
27
; a data control unit
29
; and an output buffer
31
. The 0° logic circuit
19
includes a read-command angle recognition circuit (0°)
35
and a counter (0°)
39
. The 180° logic circuit
21
includes a read-command angle recognition circuit (180°)
37
and a counter (180°)
41
.
Each of the clock buffers
7
and
8
is connected to the pads
1
and
3
, the pad
1
supplied with an external clock signal ck, and the pad
3
supplied with an external clock signal/ck. The command buffer
9
is connected to the pad
5
supplied with a command com. The frequency divider
11
is connected to the clock buffers
7
and
8
. The command recognition unit
13
is connected to the clock buffer
7
and the command buffer
9
. The DLL circuit
15
is connected to the frequency divider
11
.
The output signal generating circuit
17
is connected to the DLL circuit
15
. Each of the 0° logic circuit
19
and the 180° logic circuit
21
is connected to the frequency divider
11
, the command recognition unit
13
and the DLL circuit
15
. The output control unit
23
is connected to the 0° logic circuit
19
and the 180° logic circuit
21
. The readout circuit
25
is connected to the command recognition unit
13
. The memory
27
is connected to the readout circuit
25
. The data control unit
29
is connected to the readout circuit
25
and the output control unit
23
. The output buffer
31
is connected to the data control unit
29
and the output signal generating circuit
17
. The pad
33
outputting data D is connected to the output buffer
31
.
Hereinafter, a description will be given, with reference to the drawings, of operations of the conventional semiconductor memory device having the above-mentioned structure. The external clock signal ck supplied to the pad
1
and the external clock signal /ck supplied to the pad
3
are buffered by the clock buffers
7
and
8
, and are supplied to the frequency divider
11
as an internal clock signal clkz from the clock buffer
7
and an internal clock signal clkx from the clock buffer
8
. Then, the frequency divider
11
divides frequencies of the internal clock signals clkz and clkx so as to generate internal clock signals clke
0
z, clke
18
z, clko
0
z and clko
18
z.
On the other hand, the command com supplied to the pad
5
is buffered by the command buffer
9
, and is supplied to the command recognition unit
13
. Then, the command recognition unit
13
generates a read-command read and supplies the read-command read to the read-command angle recognition circuit (0°)
35
, the read-command angle recognition circuit (180°)
37
and the readout circuit
25
. The read-command angle recognition circuit (0°)
35
detects whether the read-command read is supplied in synchronization with the internal clock signal clke
0
z, and supplies an output control signal to the output control unit
23
. The read-command angle recognition circuit (180°)
37
detects whether the read-command read is supplied in synchronization with the internal clock signal clke
18
z, and supplies an output control signal to the output control unit
23
. In this course, a phase of the internal clock signal clke
18
z is different to a phase of the internal clock signal clke
0
z by 180°.
The DLL circuit
15
delays the internal clock signals clke
0
z, clke
18
z, clko
0
z and clko
18
z generated by the frequency divider
11
by a predetermined time so as to generate internal clock signals oclke
0
z, oclke
18
z, oclko
0
z and oclko
18
z which seem as if being a transmission time T
AC
ahead of the internal clock signals clke
0
z, clke
18
z, clko
0
z and clko
18
z in phases, the transmission time T
AC
corresponding to a path
43
from the DLL circuit
15
to the pad
33
.
Hereinafter, a description will be given, with reference to
FIG. 2
, of data-read operations of the conventional semiconductor memory device shown in FIG.
1
.
FIG. 2
is a waveform diagram indicating operations of the conventional semiconductor memory device. The description will be made of a case where a latency is six. That is, as indicated by FIG.
2
-(
a
) and FIG.
2
-(
m
), data Dn (n is a natural number) are output from the pad
33
at a time To which is six periods (clocks) of the external clock signal ck behind a time Ti at which a read-command read is supplied to the pad
5
.
First, as shown by waveforms
46
indicated by FIG.
2
-(
b
) to FIG.
2
-(
e
), the internal clock signals clke
0
z, clke
18
z, clko
0
z and clko
18
z are generated by the frequency divider
11
dividing by two the frequencies of the internal clock signals clkz and clkx based on the external clock signal ck. Waveforms
44
indicate the internal clock signals clke
0
z and clke
18
z being in synchronization with the external clock signal ck. Waveforms
45
indicate the internal clock signals clko
0
z and clko
18
z in being synchronization with the external clock signal /ck reverse to the external clock signal ck. The internal clock signals clke
18
z and clko
18
z are different in phases to the internal clock signals clke
0
z and clko
0
z by 180°, respectively.
Therefore, as indicated by FIG.
2
-(
b
) and FIG.
2
-(
c
), the internal clock signal clke
0
z, for example, comprises only even-numbered clocks of the external clock signal ck, and the internal clock signal clke
18
z, for example, comprises only odd-numbered clocks of the external clock signal ck.
Waveforms
47
indicate the signals delayed by the DLL circuit
15
Waveforms
48
correspond to the waveforms
44
, and waveforms
49
correspond to the waveforms
45
. That is, a clock numbered
4
of the internal clock signal clke
0
z indicated by FIG.
2
-(
b
), for example, is delayed by the DLL circuit
15
by a predetermined time to become a clock numbered
6
of the internal clock signal oclke
0
z indicated by FIG.
2
-(
f
).
On the other hand, the read-command angle recognition circuit (0°)
35
recognizes a reception of the read-command read with a phase difference 0° to the external clock signal ck based on the supplied internal cloc
LandOfFree
Semiconductor memory device outputting data according to a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device outputting data according to a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device outputting data according to a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2868388