Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-06-28
2002-05-21
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S752000, C257S795000, C257S758000, C257S734000
Reexamination Certificate
active
06392300
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-181878, filed Jun. 28, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and particularly to a semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire.
As the density of a semiconductor memory and a capacity thereof have been increased, the memory chip as a whole cannot be completely defect-free. Therefore, it is common knowledge to use a redundancy structure incorporating a defect relief circuit in a memory LSI and an LSI on which a memory and a logic circuit are mixed.
When a defective cell is replaced by a spare cell, first, in general, the address of the defective cell is stored in a memory, thereafter a fuse constituted of a wiring layer made of polysilicon or aluminum is blown by a laser, and a spare cell to be used in place of the defective cell is selected. To blow the fuse, an alignment mark for positioning the laser is formed of the uppermost metal wire layer.
FIGS. 1
to
9
are cross-sectional views showing a conventional process for manufacturing an LSI having a four-layer metal wiring structure in which alignment marks are formed.
First, as shown in
FIG. 1
, an element isolating region
13
is formed in a silicon substrate
11
. Then, a passive element (e.g., a resistor) and an active element (e.g., a MOSFET), made of a diffusion layer
14
, are formed in a region other than the element isolating region
13
. A reference numeral
15
denotes a gate electrode of the MOSFET. An inter-chip region
12
later serves as a dicing line. The aforementioned alignment marks are located above the dicing line region
12
.
Then, as shown in
FIG. 2
, a first interlayer insulating film
16
made of BPSG film is deposited on the substrate, and flattened by means of CMP (chemical mechanical polishing). Thereafter, a first contact hole is opened by photolithography. The first contact hole is filled with first tungsten
17
by CVD (chemical vapor deposition). Further, a first aluminum layer
18
is deposited on the overall surface of the structure. The first aluminum layer
18
is patterned into a predetermined shape by photolithography.
Subsequently, as shown in
FIG. 3
, a second interlayer insulating film
19
made of SiO
2
is deposited, and flattened by CMP. Then, a second contact hole is opened by photolithography. The second contact hole is filled with second tungsten
20
by CVD. Further, a second aluminum layer
21
is deposited on the overall surface of the structure. The second aluminum layer
21
is patterned into a predetermined shape by photolithography.
Subsequently, as shown in
FIG. 4
, a third interlayer insulating film
22
made of SiO
2
is deposited, and flattened by CMP. Then, a third contact hole is opened by photolithography. The third contact hole is filled with third tungsten
23
by CVD. Further, a third aluminum layer
24
is deposited on the overall surface of the structure. The third aluminum layer
24
is patterned into a predetermined shape by photolithography.
Thereafter, as shown in
FIG. 5
, a fourth interlayer insulating film
25
made of SiO
2
is deposited, and flattened by CMP. Then, a fourth contact hole is opened by photolithography. The fourth contact hole is filled with fourth tungsten
26
by CVD. Further, a fourth aluminum layer is deposited on the overall surface of the structure. The fourth aluminum layer is patterned into a predetermined shape by photolithography. As a result, a metal fuse (not shown) or a bonding pad
27
B is formed from a part of the fourth aluminum layer. An alignment mark
27
A is also formed from a part of the fourth aluminum layer.
Then, a s shown in
FIG. 6
, a passivation film
28
made of Si
3
N
4
is deposited. A part of the passivation film
28
on the bonding pad
27
B is etched by photolithography, thereby forming an opening through which the bonding pad
27
B is exposed. At this time, a part of the passivation film
28
on the alignment mark is also etched to prevent cracking. As a result of this etching process, the alignment mark
27
A is exposed and a part of the fourth interlayer insulating film
25
around the alignment mark
27
A is over-etched.
In the pad opening step as described above, when the alignment mark
27
A is exposed and the part of the fourth interlayer insulating film
25
around the alignment mark
27
A is over-etched, the alignment mark
27
A may probably be removed in subsequent steps, as shown in FIG.
7
. If the alignment mark
27
A is removed, fuse-blow cannot be performed, since the alignment mark
27
A, for use in positioning the laser when the fuse is blown, cannot be detected.
Further, if a bump (electrode) forming step is performed after the step show n in
FIG. 6
, another problem may arise, which will be described below with reference to
FIGS. 8 and 9
.
After the step shown in
FIG. 6
, a barrier metal
30
made of a Ti/Ni/Pd laminated film is deposited, as shown in FIG.
8
. Further, photoresist
31
is applied to the overall surface, and thereafter opened to expose that portion of the barrier metal
30
on the bonding pad
27
B on which a bump is to be formed. Then, an Au bump
32
is grown on the portion of the barrier metal
30
on the bonding pad
27
B by electrolytic plating or the like.
Thereafter, as shown in
FIG. 9
, the photoresist
31
is removed. Then, the barrier metal
30
exposed on the passivation film
28
is removed by a solution of aqua regia, ethylene-diamine-tetraacetic acid, or the like. The Au bump
32
is maintained.
Since the alignment mark
27
A made of only the fourth aluminum layer is electrically floating, it is generally charged up in the electrolytic plating step or the like. In this case, when the barrier metal
30
is removed by the aforementioned solution of aqua regia or ethylene-diamine-tetraacetic acid, the alignment mark
27
A (aluminum) under the barrier metal
30
is also undesirably etched. As a result, the alignment mark
27
A is etched as if it were a corroded alignment mark
33
. When fuse-blow is to be performed, the alignment mark
33
in the corroded state cannot be detected. In this case, since the alignment mark
33
for positioning the laser cannot be detected, fuse-blow cannot be performed.
As described above, in the conventional semiconductor device, the alignment mark
27
A is exposed in the pad opening step and the insulating film around the alignment mark
27
A is inevitably over-etched in the pad opening step. Therefore, the alignment mark may be easily removed in the subsequent steps. If the alignment mark is removed, when fuse-blow is to be performed, a problem arises, that is, the alignment mark for positioning the laser cannot be detected, and fuse-blow cannot be performed.
Further, in the bump forming step, when barrier metal exposed in a region other than the bump electrode portion is removed by a solution, the alignment mark under the barrier metal is etched as if it were corroded. Therefore, when fuse-blow is to be performed, a problem arises, that is, the alignment mark cannot be detected and fuse-blow cannot be performed.
BRIEF SUMMARY OF THE INVENTION
The present invention was made to solve the above problems. It is accordingly an object of the present invention to provide a semiconductor device, even if an alignment mark is exposed and an insulating film around the alignment mark is over-etched in a pad opening step, which semiconductor device can prevent the alignment mark from being removed in the subsequent steps and can detect the alignment mark in fuse-blow.
Another object of the present invention is to provide a semiconductor device, which can prevent an alignment mark under a barrier metal from being etched, when the barrier metal exposed in a region other than a bump electrode region is removed by a solution, and which can detect the alignment mark in fuse-blow.
To achieve the above object, a s
Kabushiki Kaisha Toshiba
Smith Matthew
Yevsikov V.
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